m36l0r7040t0 STMicroelectronics, m36l0r7040t0 Datasheet

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m36l0r7040t0

Manufacturer Part Number
m36l0r7040t0
Description
128 Mbit Multiple Bank, Multi-level, Burst Flash Memory And 16 Mbit Psram, 1.8v Supply, Multi-chip Package
Manufacturer
STMicroelectronics
Datasheet

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Quantity
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Part Number:
m36l0r7040t0ZAQ
Manufacturer:
ST
Quantity:
20 000
Part Number:
m36l0r7040t0ZAQF
Manufacturer:
ST
Quantity:
5 572
FEATURES SUMMARY
FLASH MEMORY
December 2004
MULTI-CHIP PACKAGE
SUPPLY VOLTAGE
ELECTRONIC SIGNATURE
PACKAGE
SYNCHRONOUS / ASYNCHRONOUS READ
SYNCHRONOUS BURST READ SUSPEND
PROGRAMMING TIME
MEMORY ORGANIZATION
DUAL OPERATIONS
SECURITY
1 die of 128 Mbit (8Mb x16, Multiple Bank,
Multi-level, Burst) Flash Memory
1 die of 16 Mbit (1Mb x16) Pseudo SRAM
V
V
Manufacturer Code: 20h
Device Code (Top Flash Configuration)
M36L0R7040T0: 88C4h
Device Code (Bottom Flash
Configuration) M36L0R7040B0: 88C5h
Compliant with Lead-Free Soldering
Processes
Lead-Free Versions
Synchronous Burst Read mode: 54MHz
Asynchronous Page Read mode
Random Access: 85ns
10µs typical Word program time using
Buffer Program
Multiple Bank Memory Array: 8 Mbit
Banks
Parameter Blocks (Top or Bottom
location)
program/erase in one Bank while read in
others
No delay between read and write
operations
64 bit unique device number
2112 bit user programmable OTP Cells
DDF
PP
128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
= 9V for fast program (12V tolerant)
= V
and 16 Mbit PSRAM, 1.8V Supply, Multi-Chip Package
DDP
= V
DDQ
= 1.7 to 1.95V
Figure 1. Package
PSRAM
BLOCK LOCKING
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ACCESS TIME: 70ns
LOW STANDBY CURRENT: 110µA
DEEP POWER DOWN CURRENT: 10µA
All blocks locked at power-up
Any combination of blocks can be locked
with zero latency
WP
Absolute Write Protection with V
F
for Block Lock-Down
M36L0R7040B0
M36L0R7040T0
TFBGA88 (ZAQ)
8 x 10mm
FBGA
PP
= V
1/18
SS

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m36l0r7040t0 Summary of contents

Page 1

... DDQ – for fast program (12V tolerant) PP ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code (Top Flash Configuration) M36L0R7040T0: 88C4h – Device Code (Bottom Flash Configuration) M36L0R7040B0: 88C5h PACKAGE – Compliant with Lead-Free Soldering Processes – Lead-Free Versions FLASH MEMORY SYNCHRONOUS / ASYNCHRONOUS READ – ...

Page 2

... M36L0R7040T0, M36L0R7040B0 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A22 Data Input/Output (DQ0-DQ15 Flash Chip Enable (E ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 F Flash Output Enable (G ) ...

Page 3

... PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline15 Table 9. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 M36L0R7040T0, M36L0R7040B0 3/18 ...

Page 4

... M36L0R7040T0, M36L0R7040B0 SUMMARY DESCRIPTION The M36L0R7040T0 and M36L0R7040B0 com- bine two memory devices in a Multi-Chip Package: a 128-Mbit, Multiple Bank Flash memory, the M30L0R7000T0 or M30L0R7000B0, and a 16- Mbit PseudoSRAM, the M69AR024B. Recom- mended operating conditions do not allow more than one memory to be active at the same time. ...

Page 5

... A3 D A17 DQ8 DQ0 M36L0R7040T0, M36L0R7040B0 A19 DDF PPF A20 DQ2 DQ10 DQ5 ...

Page 6

... M36L0R7040T0, M36L0R7040B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Names, for a brief overview of the signals connect this device. Address Inputs (A0-A22). Addresses are common inputs for the Flash memory and the PSRAM components. The other lines (A20-A22) are inputs for the Flash memory component only. ...

Page 7

... V Supply Voltage. V provides the power DDQ DDQ supply for the Flash Memory I/O pins. This allows all Outputs to be powered independently of the Flash Memory core power supply, V M36L0R7040T0, M36L0R7040B0 at V and E2 V Program Supply Voltage PPF Flash control input and a Flash power supply pin. ...

Page 8

... M36L0R7040T0, M36L0R7040B0 FUNCTIONAL DESCRIPTION The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by three Chip En- able inputs: E for the Flash memory and for the PSRAM. P Recommended operating conditions do not allow more than one device to be active at a time. The Figure 4 ...

Page 9

... IH Any PSRAM mode is allowed M36L0R7040T0, M36L0R7040B0 ,UB DQ15-DQ0 Flash Data Out Flash Data In Flash Data Out or Hi-Z Hi-Z Hi-Z Hi-Z PSRAM data out PSRAM data in IH ...

Page 10

... Mbit Flash memory. For detailed information on how to use the devices, PSRAM COMPONENT The M36L0R7040T0 and M36L0R7040B0 contain a 16 Mbit PSRAM. For detailed information on how to use the device, see the M69AR024B datasheet 10/18 M30L0R7000(T/B)0 datasheet which is available from the internet site http://www.st.com or from see the your local STMicroelectronics distributor ...

Page 11

... Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Min –25 –25 –65 –0.2 –0.2 –0.2 PPFH M36L0R7040T0, M36L0R7040B0 Value Unit Max 85 85 125 (1) 3.3 2.5 14 100 mA ...

Page 12

... M36L0R7040T0, M36L0R7040B0 DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Table 4. Operating and AC Measurement Conditions Parameter ...

Page 13

... I V Supply Current (Read) PP2 PPF (1) V Supply Current (Standby) I PPF PP3 Note: 1. Sampled only, not 100% tested Dual Operation current is the sum of read and program or erase currents. DDF M36L0R7040T0, M36L0R7040B0 Test Condition Min DDQ OUT DDQ ...

Page 14

... M36L0R7040T0, M36L0R7040B0 Table 7. Flash Memory DC Characteristics - Voltages Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Program Voltage-Logic PP1 PPF V V Program Voltage Factory PPH PPF V Program or Erase Lockout PPLK V V Lock Voltage ...

Page 15

... A1 A2 0.850 b 0.350 D 8.000 D1 5.600 ddd E 10.000 E1 7.200 E2 8.800 e 0.800 FD 1.200 FE 1.400 FE1 0.600 SD 0.400 SE 0.400 M36L0R7040T0, M36L0R7040B0 Min Max Typ 1.200 0.200 0.0335 0.300 0.400 0.0138 7.900 8.100 0.3150 0.2205 0.100 9.900 10.100 0.3937 0.2835 0.3465 – ...

Page 16

... M36L0R7040T0, M36L0R7040B0 PART NUMBERING Table 10. Ordering Information Scheme Example: Device Type M36 = Multi-Chip Package (Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture Die Operating Voltage 1.7 to 1.95V DDF DDP DDQ Flash 1 Density 7 = 128 Mbit Flash 2 Density ...

Page 17

... First Issue TFBGA88 package specifications updated. TFBGA88 package fully compliant with the ST ECOPACK specification. 06-Dec-2004 2.0 Flash memory and PSRAM data updated to revision 1.0 of M30L0R7000x0 datasheet and revision 6.0 of M69AR024B datasheet. Document status promoted from Target Specification to full Datasheet. M36L0R7040T0, M36L0R7040B0 Revision Details 17/18 ...

Page 18

... M36L0R7040T0, M36L0R7040B0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...

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