th50vsf2583aasb TOSHIBA Semiconductor CORPORATION, th50vsf2583aasb Datasheet - Page 30

• Manufacturer Part Number: th50vsf2583aasb
• Description: Sram Flash Memory Mixed Multi-chip Package
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DQ3 (Block Erase timer)
command cycle. DQ3 outputs a 0 for the duration of the Block Erase Hold Time and a 1 when the Block Erase
operation starts. Additional Block Erase commands can only be accepted during the Block Erase Hold Time.
Each Block Erase command input within the hold time resets the timer, allowing additional blocks to be marked
for erasing. DQ3 outputs a 1 if the Program or Erase operation fails.
DQ2 (Toggle bit 2)
device is in Erase Suspend Mode.
Now 1 will be output from non-selected blocks; thus, the selected block can be ascertained. If data is read
continuously from the block selected for Auto Block Erase while the device is in Erase Suspend Mode, the DQ2
output will toggle. Because the DQ6 output is not toggling, it can be determined that the device is in Erase
Suspend Mode. If data is read from the address to which data is being written during Erase Suspend in
Programming Mode, DQ2 will output a 1.
(Busy state) indicates that an Auto-Program or auto-erase operation is in progress. A 1 (Ready state) indicates
that the operation has finished and that the device can now accept a new command.
an operation has failed.
1 during an Erase Suspend operation. The output buffer for the
allowing a wired-OR connection. A pull-up resistor must be inserted between V
RY
The Block Erase operation starts 50 µs (the Erase Hold Time) after the rising edge of WE in the last
DQ2 is used to indicate which blocks have been selected for Auto Block Erase or to indicate whether the
If data is read continuously from the selected block during an Auto Block Erase, the DQ2 output will toggle.
The TH50VSF2582/2583AASB has a
During an Auto Block Erase operation, commands other than Erase Suspend are ignored.
RY
/
BY
/
BY
(READY /
outputs a 0 after the rising edge of WE in the last command cycle.
BUSY
)
RY
/
BY
signal to indicate the device status to the host processor. A 0
RY
/
TH50VSF2582/2583AASB
BY
pin is an open-drain type circuit,
CC
and the
RY
2001-10-25 30/50
/
BY
RY
RY
/
outputs a 0 when
BY
/
BY
pin.
outputs a