th50vsf2583aasb TOSHIBA Semiconductor CORPORATION, th50vsf2583aasb Datasheet
th50vsf2583aasb
Available stocks
Related parts for th50vsf2583aasb
th50vsf2583aasb Summary of contents
Page 1
... Erase and Program cycles for flash memory • SRAM • Boot block architecture for flash memory TH50VSF2582AASB: Top boot block 262,144 words of 16 bits TH50VSF2583AASB: Bottom boot block 524,288 words of 8 bits Package • 524,288 words of 8 bits P-FBGA69-1209-0.80A3: 0.31 g (typ.) PIN NAMES 6 7 ...
Page 2
PIN ASSIGNMENT (TOP VIEW) • CIOF = V , CIOS = V (×16, × /ACC RESET A18 ...
Page 3
BLOCK DIAGRAM A0~A21 WP /ACC RESET CEF CIOF CE2S UB LB CIOS MODE SELECTION OPERATION MODE CEF L Flash Read L H SRAM Read Flash Write L H ...
Page 4
... ID CODE TABLE CODE TYPE Manufacturer Code TH50VSF2582AASB Device Code TH50VSF2583AASB Verify Block Protect Notes (1) DQ8~DQ15 are Hi-Z in Byte mode (2) BA: Block Address (3) 0001H - Protected Block 0000H - Unprotected Block A20~A12 ( TH50VSF2582/2583AASB A1 A0 CODE (HEX) ...
Page 5
... Bank Address and ID Read Address (A6, A1, A0) Bank Address = A20~A15 Manufacturer Code = ( Device Code = ( (5) ID: ID Data 0098H - Manufacturer Code 009AH - Device Code (TH50VSF2582AASB) 009CH - Device Code (TH50VSF2583AASB) 0001H - Protected Block SECOND BUS THIRD BUS WRITE CYCLE WRITE CYCLE Data Addr ...
Page 6
BLOCK ERASE ADDRESS TABLES (1) TH50VSF2582AASB (top boot block) BANK BLOCK # # A20 A19 A18 A17 A16 A15 A14 A13 A12 BA0 L BA1 L BA2 L BA3 L BK0 BA4 L BA5 L BA6 L BA7 L BA8 ...
Page 7
BANK BLOCK BANK ADDRESS # # A20 A19 A18 A17 A16 A15 A14 A13 A12 BA32 H L BA33 H L BA34 H L BA35 H L BK4 BA36 H L BA37 H L BA38 H L BA39 H L ...
Page 8
BANK BLOCK BANK ADDRESS # # A20 A19 A18 A17 A16 A15 A14 A13 A12 BA63 H H BA64 H H BA65 H H BA66 H H BK8 BA67 H H BA68 H H BA69 H H BA70 H H ...
Page 9
... TH50VSF2583AASB (bottom boot block) BANK BLOCK BANK ADDRESS # # A20 A19 A18 A17 A16 A15 A14 A13 A12 BA0 L L BA1 L L BA2 L L BA3 L L BK0 BA4 L L BA5 L L BA6 L L BA7 L L BA8 L L BA9 L L BA10 L L BK1 ...
Page 10
BANK BLOCK BANK ADDRESS # # A20 A19 A18 A17 A16 A15 A14 A13 A12 BA31 L H BA32 L H BA33 L H BA34 L H BK4 BA35 L H BA36 L H BA37 L H BA38 L H ...
Page 11
BANK BLOCK BANK ADDRESS # # A20 A19 A18 A17 A16 A15 A14 A13 A12 BA63 H H BA64 H H BA65 H H BA66 H H BK8 BA67 H H BA68 H H BA69 H H BA70 H H ...
Page 12
... BA0~BA7 64 Kbytes BA8~BA15 64 Kbytes BA16~BA23 64 Kbytes BA24~BA31 64 Kbytes BA32~BA39 64 Kbytes BA40~BA47 64 Kbytes BA48~BA55 64 Kbytes BA56~BA62 64 Kbytes BA63~BA70 8 Kbytes (2) TH50VSF2583AASB (bottom boot block) BLOCK SIZE BLOCK # BYTE MODE BA0~BA7 8 Kbytes BA8~BA14 64 Kbytes BA15~BA22 64 Kbytes BA23~BA30 64 Kbytes BA31~BA38 64 Kbytes BA39~BA46 64 Kbytes BA47~BA54 64 Kbytes ...
Page 13
ABSOLUTE MAXIMUM RATINGS SYMBOL Supply Voltage CC CCs CCf (1) V Input Voltage IN V Input/Output Voltage DQ T Operating Temperature opr P Power Dissipation D T Soldering Temperature (10s) solder I Output Short Circuit Current OSHORT ...
Page 14
RECOMMENDED DC OPERATING CONDITIONS SYMBOL V /V Power Supply Voltage CCs CCf V Input High-Level Voltage IH V Input Low-Level Voltage IL V Data Retention Voltage for SRAM DH V Flash Low-Lock Voltage LKO V High Voltage for WP ACC ...
Page 15
V DC CHARACTERISTICS SYMBOL PARAMETER I Input Leakage Current IL I SRAM Output High Current SOH I SRAM Output Low Current SOL I Flash Output High Current (TTL) V FOH1 Flash Output High Current ...
Page 16
V AC CHARACTERISTICS Read cycle SYMBOL t Read Cycle Time RC t Address Access Time ACC t Chip Enable ( CO1 t Chip Enable (CE2S) Access Time CO2 t Output ...
Page 17
AC CHARACTERISTICS (FLASH MEMORY) READ CYCLE SYMBOL PARAMETER t Read Cycle Time RC t Address Access Time ACC t CEF Access Time Access Time OE t CEF to Output Low-Z CEE Output Low-Z OEE ...
Page 18
COMMAND WRITE/PROGRAM/ERASE CYCLE SYMBOL PARAMETER t Command Write Cycle Time CMD t Address Set-up Time / BYTE Set-up Time AS t Address Hold Time / BYTE Hold Time AH t Address Hold Time from WE High level AHW t Data ...
Page 19
SIMULTANEOUS READ/WRITE OPERATION The TH50VSF2582/2583AASB features a Simultaneous Read/Write operation. The Simultaneous Read/Write operation enables the device to simultaneously write data to or erase data from a bank while reading data from another bank. The TH50VSF2582/2583AASB has a total of ...
Page 20
ID Read Mode ID Read mode is used to read the device maker code and device code. The mode is useful for EPROM programmers to automatically identify the device type. In this method, simultaneous operation can be performed. Inputting an ...
Page 21
Command Write The TH50VSF2582/2583AASB uses the standard JEDEC control commands for a single-power supply 2 E PROM. A Command Write is executed by inputting the address and data into the Command Register. The command is written by inputting a pulse ...
Page 22
Auto-Program Mode The TH50VSF2582/2583AASB can be programmed in either byte or word units. Auto-Program Mode is set using the Program command. The program address is latched on the falling edge of the WE signal and data is latched on the ...
Page 23
Program Suspend/Resume Mode Program Suspend is used to enable Data Read by suspending the Write operation. The device accepts a Program Suspend command in Write Mode (including Write operations performed during Erase Suspend) but ignores the command in other modes. ...
Page 24
Auto Block Erase / Auto Multi-Block Erase Modes The Auto Block Erase Mode and Auto Multi-Block Erase Mode are set using the Block Erase command. The block address is latched on the falling edge of the WE signal in the ...
Page 25
Block Protection Block Protection is a function to disable write and erase in block units. Applying V to RESET and inputting the Block Protect command performs block protection. The first cycle of ID the command sequence is the Setup command. ...
Page 26
... To exit Hidden ROM Mode, use the Hidden ROM Mode Exit command. This will return the device to Read Mode. HIDDEN ROM AREA ADDRESS TABLE BOOT BLOCK TYPE ARCHITECTURE TH50VSF2582AASB TOP BOOT BLOCK TH50VSF2583AASB BOTTOM BOOT BLOCK is input to RESET . Once the block has been protected, protection cannot be BYTE MODE ADDRESS RANGE 3F0000H~3FFFFFH 64 Kbytes 000000H~00FFFFH ...
Page 27
COMMON FLASH MEMORY INTERFACE (CFI) The TH50VSF2520/2583AASB conforms to the CFI specifications. To read information from the device, input the Query command followed by the address. In Word Mode DQ8~DQ15 all output 0s. To exit this mode, input the Reset ...
Page 28
... Block Protect/Unprotect scheme Simultaneous operation 0: Not supported 1: Supported Burst Mode 0: Not supported Page Mode 0: Not supported V (min) voltage ACC DQ7~DQ4 DQ3~DQ0: 100 mV V (max) voltage ACC DQ7~DQ4 DQ3~DQ0: 100 mV Top/Bottom Boot Block Flag 2: TH50VSF2582AASB 3: TH50VSF2583AASB Program suspend 0: Not supported 1: Supported 2001-10-25 28/50 ...
Page 29
HARDWARE SEQUENCE FLAGS FOR FLASH MEMORY The TH50VSF2582/2583AASB has a Hardware Sequence flag which allows the device status to be determined during an auto mode operation. The output data is read out using the same timing as that used when ...
Page 30
DQ3 (Block Erase timer) The Block Erase operation starts 50 µs (the Erase Hold Time) after the rising edge the last command cycle. DQ3 outputs a 0 for the duration of the Block Erase Hold Time and ...
Page 31
DATA PROTECTION The TH50VSF2582/2583AASB includes a function which guards against malfunction or data corruption. Protection against Program/Erase Caused by Low Supply Voltage To prevent malfunction at power-on or power-down, the device will not accept commands while ...
Page 32
TIMING DIAGRAMS FLASH READ/ID READ OPERATION Address CEF OEH D OUT SRAM READ CYCLE (see Note 1) Address CE2S Hi-Z OUT Data invalid t ...
Page 33
SRAM WRITE CYCLE Address CE2S See Note 2 OUT D See Note SRAM WRITE CYCLE 2 ( Address CE2S CE ...
Page 34
SRAM WRITE CYCLE 3 (CE2S-CONTROLLED) (see Note 4) Address CE2S OUT D See Note SRAM WRITE CYCLE 4 ( Address CE2S UB ...
Page 35
FLASH COMMAND WRITE OPERATION This is the timing of the Command Write Operation. The timing which is described in the following pages is essentially the same as the timing shown on this page. • WE Control Address CEF WE D ...
Page 36
FLASH ID READ OPERATION (Input command sequence) Address 555H t CMD CEF OE t OES WE D AAH IN D OUT Read Mode (input of ID Read command sequence) (Continued) 555H Address t CMD CEF AAH IN ...
Page 37
FLASH AUTO-PROGRAM OPERATION ( Address 555H t CMD CEF OE t OES WE D AAH IN D OUT t VCS V CCf Note: Word Mode address shown. PA: Program address PD: Program data FLASH AUTO CHIP ERASE / AUTO BLOCK ...
Page 38
FLASH AUTO-PROGRAM OPERATION ( 555H Address t CMD CEF OE t OES AAH D OUT t VCS V CCf Note: Word Mode address shown. PA: Program address PD: Program data FLASH AUTO CHIP ERASE / AUTO BLOCK ...
Page 39
FLASH PROGRAM/ERASE SUSPEND OPERATION Address BK CEF B0H IN D Hi-Z OUT Program/Erase Mode RA: Read address BK: Bank address FLASH PROGRAM/ERASE RESUME OPERATION RA Address CEF OE t OES WE t DF1 t ...
Page 40
FLASH DURING AUTO-PROGRAM/ERASE OPERATION CEF FLASH HARDWARE RESET OPERATION WE RESET FLASH READ AFTER RESET Address RESET D OUT Command input sequence READY t RC ...
Page 41
FLASH HARDWARE SEQUENCE FLAG ( Last Address Command Address t CMD Last D Command IN Data DQ7 DQ0~DQ6 t BUSY PA: Program address BA: Block address FLASH HARDWARE SEQUENCE FLAG (Toggle bit) Address CEF ...
Page 42
FLASH BLOCK PROTECT OPERATION Address t CMD CEF VPS RESET D 60H IN D OUT BA: Block address Address of next block *: 01H indicates that block ...
Page 43
TIMING FOR SWITCHING BETWEEN FLASH AND SRAM MODES CEF CE2S Notes: (1) WE remains High during a Read cycle. ( goes Low (or CE2S goes High) at the same time as or after ...
Page 44
SRAM DATA RETENTION CHARACTERISTICS SYMBOL V Data Retention Supply Voltage for SRAM DH I SRAM Standby Current CCS4 t Chip-Deselect-to-Data-Retention-Mode Time CDR t Recovery Time r (1) Read cycle time -CONTROLLED DATA RETENTION MODE (see Note 1) ...
Page 45
FLOWCHARTS OF FLASH MEMORY OPERATIONS Auto-Program Address = Address + 1 Note: The above command sequence takes place in Word Mode. Start Auto-Program Command Sequence (see below) DATA Polling or Toggle Bit No Last Address? Yes Auto-Program Completed Auto-Program Command ...
Page 46
Fast Program Address = Address + 1 Fast Program Set Command Sequence (address/data) 555H/AAH 2AAH/55H 555H/20H TH50VSF2582/2583AASB Start Fast Program Set Command Sequence (see below) Fast Program Command Sequence (see below) DATA Polling or Toggle Bit No Last Address? Yes ...
Page 47
Auto Erase Auto Chip Erase Command Sequence (address/data) 555H/AAH 2AAH/55H 555H/80H 555H/AAH 2AAH/55H 555H/10H Note: The above command sequence takes place in Word Mode. Start Auto Erase Command Sequence (see below) DATA Polling or Toggle Bit Auto Erase Completed Auto ...
Page 48
DQ7 DATA Polling Start Read Byte (DQ0~DQ7) Addr DQ7 = Data? No DQ5 = 1? Read Byte (DQ0~DQ7) Addr DQ7 = Data? Fail DQ6 Toggle Bit Start Read Byte (DQ0~DQ7) Addr DQ6 = Toggle? ...
Page 49
Block Protect RESET = V Wait for 4 µs PLSCNT = 1 Block Protect Command First Bus Write Cycle (XXXH/60H) Set up Address Addr. = BPA Block Protect Command Second Bus Write Cycle Wait for 100 µs Block Protect Command ...
Page 50
PACKAGE DIMENSIONS TH50VSF2582/2583AASB Unit: mm 2001-10-25 50/50 ...
Page 51
... Copyright ⓒ Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www.AllDataSheet.com 100% Free DataSheet Search Site. Fast Search System. www.AllDataSheet.com Free Download. No Register. ...