am42bds640ag Meet Spansion Inc., am42bds640ag Datasheet - Page 27

• Manufacturer Part Number: am42bds640ag
• Description: 64 Megabit 4 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory And 16 Mbit 1 M ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

the system was writing to the read mode. Once erasure
begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins (prior to the third cycle).
This resets the bank to which the system was writing to
the read mode. If the program command sequence is
written to a bank that is in the Erase Suspend mode,
writing the reset command returns that bank to the
erase-suspend-read mode. Once programming
begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to the read mode. If a bank entered
the autoselect mode while in the Erase Suspend mode,
writing the reset command returns that bank to the
erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to the
read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).
The reset command is used to exit the sector
lock/unlock sequence.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Table 14, “Command Definitions,” on page 30
the address and data requirements. The autoselect
command sequence may be written to an address
within a bank that is either in the read or erase-sus-
pend-read mode. The autoselect command may not be
written while the device is actively programming or
erasing in the other bank.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the
autoselect command. The bank then enters the
autoselect mode. No subsequent data will be made
available if the autoselect data is read in synchronous
mode. The system may read at any address within the
same bank any number of times without initiating
another autoselect command sequence. The following
table describes the address requirements for the
various autoselect functions, and the resulting data. BA
represents the bank address, and SA represents the
sector address. The device ID is read in three cycles.
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P R E L I M I N A R Y
shows
Am42BDS640AG
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
Program Command Sequence
Programming is a four-bus-cycle operation. The
program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin.
and data requirements for the program command
sequence.
When the Embedded Program algorithm is complete,
that bank then returns to the read mode and addresses
are no longer latched. The system can determine the
status of the program operation by monitoring DQ7 or
DQ6/DQ2. Refer to the
section on page 31
status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should be
reinitiated once that bank has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from
“0” back to a “1.” Attempting to do so may cause that
bank to set DQ5 = 1, or cause the DQ7 and DQ6 status
bit to indicate the operation was successful. However,
a succeeding read will show that the data is still “0.”
Only erase operations can convert a “0” to a “1.”
Manufacturer ID
Device ID, Word 1
Device ID, Word 2,
Top Boot
Device ID, Word 2,
Bottom Boot
Device ID, Word 3
Sector Block
Lock/Unlock
Handshaking
Description
Table 13. Device IDs
section for information on these
(BA) + 00h
(BA) + 01h
(BA) + 0Eh
(BA) + 0Eh
(BA) + 0Fh
(SA) + 02h
(BA) + 03h
Address
“Flash Write Operation Status”
Table 14
November 1, 2002
shows the address
2204h (1.8 V V
2224h (1.8 V V
0000 (unlocked)
42h (standard)
0001 (locked),
43h (reduced
Read Data
wait-state),
227Eh
0001h
2201h
IO
IO
)
)