am42bds640ag Meet Spansion Inc., am42bds640ag Datasheet
am42bds640ag
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am42bds640ag Summary of contents
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... Am42BDS640AG Data Sheet Continuity of Specifications Continuity of Ordering Part Numbers For More Information Publication Number 26445 Revision B Amendment 0 Issue Date November 1, 2002 ...
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... PRELIMINARY Am42BDS640AG Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29BDS640G 64 Megabit ( 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory and 16 Mbit ( 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 1.65 to 1.95 volt High performance — Access time as fast Package — ...
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... AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection. Am42BDS640AG de WP# locks sec- IL November 1, 2002 ...
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... Figure 17. Reduced Wait-State Handshaking Burst Mode Read Starting at an Odd Address............................................................ 46 Asynchronous Read ............................................................... 47 Figure 18. Asynchronous Mode Read with Latched Addresses .... 47 Figure 19. Asynchronous Mode Read............................................ 48 Figure 20. Reset Timings ............................................................... 49 Erase/Program Operations ..................................................... 50 Figure 21. Asynchronous Program Operation Timings .................. 51 Figure 22. Alternate Asynchronous Program Operation Timings... 52 Figure 23. Synchronous Program Operation Timings.................... 53 Am42BDS640AG 3 ...
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... Flash Latchup Characteristics Package Pin Capacitance . . . . . . . . . . . . . . . . . . 68 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 68 SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 69 Figure 39. CE1#s Controlled Data Retention Mode....................... 69 Figure 40. CE2s Controlled Data Retention Mode......................... 69 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 70 FSC093—93-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............ 70 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 71 Revision A (May 20, 2002) ..................................................... 71 Am42BDS640AG . 68 November 1, 2002 ...
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... Am42BDS640AG CC, IO 1.65 – 1. Reduced IACC ) Reduced IACC ) ) ACC V f RDY 64 M Bit Flash Memory DQ15 to DQ0 Bit DQ15 to DQ0 Static RAM Am42BDS640AG 54 MHz 40 MHz D8, D9 C8, C9 87.5 95 106 120 13 13 DQ15 to DQ0 5 ...
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... State CLK Control A21– RDY Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Logic Y-Decoder Timer X-Decoder Burst Address Counter Am42BDS640AG DQ15–DQ0 Input/Output Buffers Data Latch Y-Gating Cell Matrix November 1, 2002 ...
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... A21–A0 A21–A0 A21–A0 November 1, 2002 Bank A Address Bank A X-Decoder Bank B Address Bank B X-Decoder Status Control X-Decoder Bank C Bank C Address X-Decoder Bank D Address Bank D Am42BDS640AG DQ15–DQ0 OE# DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 7 ...
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... DQ11 NC DQ5 DQ14 SSOP). The package and/or data integrity may be compromised if the package body is exposed to tem- peratures above 150 C for prolonged periods of time. Am42BDS640AG A10 Flash only NC B10 B9 SRAM only Shared NC D9 A15 E9 A21 F9 F10 ...
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... November 1, 2002 WP# ACC LOGIC SYMBOL Am42BDS640AG High = device ignores address in- puts = Hardware write protect input disables program and erase func- tions in the two outermost sectors. Should for all other condi- IH tions. ...
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... Valid Combinations Order Number Am42BDS640AGTD8I Am42BDS640AGBD8I Am42BDS640AGTD9I Am42BDS640AGBD9I Am42BDS640AGTC8I Am42BDS640AGBC8I Am42BDS640AGTC9I Am42BDS640AGBC9I Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. 10 ...
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... The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the re- sulting output. The following subsections describe each of these operations in further detail. Am42BDS640AG 11 ...
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... See the Lock/Unlock Command at the same ACC = WP boot) are protected aforementioned sectors depends on whether they were last protected or unprotected using the method described in Lock/Unlock Command Sequence” floating or unconnected. Am42BDS640AG LB#s UB#s DQ RESET# CLK [7–0] (Note 4) I ...
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... As an example: if the starting address in the 8-word mode is 39h, the address range to be read would Am42BDS640AG Table 10. 12. 0-7h, 8-Fh, 10-17h, ... 0-Fh, 10-1Fh, 20-2Fh, ... ...
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... Accelerated Program Operation The device offers accelerated program operations through the ACC function. ACC is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts V matically enters the aforementioned Unlock Bypass Am42BDS640AG , and OE and OE when writing Table 8, “ ...
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... The device offers two types of data protection at the sector level: or the CLK ACC The sector lock/unlock command sequence dis- ables or re-enables both program and erase opera- tions in any sector. Am42BDS640AG , the RP ± 0.2 V, the device RESET# is held CC4 ± 0.2 V, the standby current will ...
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... Table 3. CFI Query Identification String Query Unique ASCII string “QRY” Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Am42BDS640AG is less than V , the device does not accept LKO is greater than V . The system ...
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... Max. number of bytes in multi-byte write = 2 (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information Am42BDS640AG N µs N µ s (00h = not supported ...
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... Bottom Boot Device, 03h = Top Boot Device Program Suspend. 00h = not supported Bank Organization Number of banks Bank A Region Information Number of sectors in bank Bank B Region Information Number of sectors in bank Bank C Region Information Number of sectors in bank Bank D Region Information Number of sectors in bank Am42BDS640AG November 1, 2002 ...
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... Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Am42BDS640AG (x16) Address Range 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh ...
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... Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Am42BDS640AG (x16) Address Range 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh ...
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... Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Am42BDS640AG (x16) Address Range 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh ...
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... Am42BDS640AG (x16) Address Range 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh ...
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... The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency. Am42BDS640AG Power-up/ Hardware Reset Asynchronous Read Mode Only ...
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... The sixteen- and thirty-two linear wrap around 5 modes operate in a fashion similar to the eight-word 40 MHz 6 mode. Table 11 shows the address bits and settings for the 7 four burst read modes MHz 8 Am42BDS640AG Typical No. of Clock Cycles after AVD# Low 40/54 MHz November 1, 2002 ...
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... Address bits are don’t cares for this command. The reset command may be written between the ). IH sequence cycles in an erase command sequence before erasing begins. This resets the bank to which Am42BDS640AG whenever there is valid data on the outputs ...
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... DQ5 = 1, or cause the DQ7 and DQ6 status bit to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” “1.” Am42BDS640AG Address Read Data (BA) + 00h ...
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... The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to the “Flash Write Operation Status” section on page 31 section for information on these status bits. Am42BDS640AG START Write Erase Command Sequence Data Poll from System Embedded ...
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... DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. Am42BDS640AG “Flash Write section for infor- November 1, 2002 ...
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... November 1, 2002 Embedded algorithm in progress Increment Address Note: See Table 14 for program command sequence. Figure 3. Program Operation Am42BDS640AG START Write Program Command Sequence Data Poll from System Program Verify Data? No ...
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... The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. See “Set Burst Mode Configuration Register Command Sequence” for details. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. Am42BDS640AG Fourth Fifth Addr Data Addr ...
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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 4. Data# Polling Algorithm Am42BDS640AG Figure 27, Yes No Yes Yes ...
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... The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress whether that sector is erase-suspended. Toggle Bit Am42BDS640AG (toggle bit Table 15, “DQ6 and DQ2 Indica- No Yes ...
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... DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). Am42BDS640AG Table 15 to compare outputs for DQ2 and Figure 5, 57, and 33 ...
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... Table 16 shows the status of DQ3 relative to the other status bits. Table 16. Write Operation Status DQ7 (Note 2) DQ6 DQ7# Toggle 0 Toggle 1 No toggle Data Data DQ7# Toggle Am42BDS640AG DQ5 DQ2 (Note 1) DQ3 (Note 2) 0 N/A No toggle 0 1 Toggle 0 N/A Toggle Data Data Data ...
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... Operating ranges define those limits between which the func- tionality of the device is guaranteed. November 1, 2002 +0.8 V –0 0.5 V –2 Figure 6. Maximum Negative Overshoot Waveform +2 +0.5 V 1.0 V Figure 7. Maximum Positive Overshoot Waveform Am42BDS640AG ...
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... min I = –100 µ min min = V max ns. Typical sleep mode current is equal to I ACC and V currents. ACC CC Am42BDS640AG Min Typ Max Unit ±1 µA ±1 µ 0.2 10 µ 3 ...
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... 0 –0 CE1#s V – 0.2 V, CE2 0.2 V (CE1#s controlled) or CE2 0.2 V (CE2s controlled), CIOs = Other input = Not 100% tested. A Am42BDS640AG Min Typ Max Unit –1.0 1.0 µA –1.0 1.0 µ 0.2 V 1.4 V – ...
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... Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am42BDS640AG Table 17. Test Specifications All speed options 1 TTL gate 0.0– ...
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... SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 10. Timing Diagram for Alternating November 1, 2002 Test Setup — t CCR t CCR Between SRAM and Flash Am42BDS640AG All Speeds Unit Min CCR t CCR 39 ...
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... Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD Max Max Max Min Min Max Max Max Max Min Min Max Min Min Min Min Min Max Am42BDS640AG D8 C8 (54 MHz) (40 MHz) Unit 87 D8, D9 C8, C9 (54 MHz) (40 MHz) Unit 106 120 ns 13 ...
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... The device is in synchronous mode. Figure 11. CLK Synchronous Burst Mode Read November 1, 2002 cycles for initial access shown IACC t ACC t OE (rising active CLK) Am42BDS640AG t CEZ 7 t BDH t BACC OEZ t RACC t ...
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... The device is in synchronous mode. 4. A17 = 0. Figure 12. CLK Synchronous Burst Mode Read cycles for initial access shown BDH IACC t ACC t t RACC OE t RDYS (Falling Active Clock) Am42BDS640AG t CEZ t BACC Hi OEZ Hi-Z November 1, 2002 ...
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... cycles for initial access shown IACC t ACC 7 cycles for initial access shown. 18.5 ns typ. (54 MHz IACC t ACC t RACC t RDYS Am42BDS640AG t CEZ 7 t BDH t BACC OEZ t RACC t RDYS t BDH t BACC Hi-Z ...
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... Figure 15. Burst with RDY Set One Cycle Before Data wait cycles for initial access shown typ. (40 MHz BDH t D0 IACC t ACC t RACC RDYS Am42BDS640AG t CEZ t BACC OEZ November 1, 2002 Hi-Z Hi-Z ...
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... CLK synchronous burst mode. Figure 16. Reduced Wait-State Handshaking Burst Mode Read November 1, 2002 cycles for initial access shown IACC t ACC OE Starting at an Even Address Am42BDS640AG t CEZ 7 t BDH t BACC OEZ t RACC t ...
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... This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under a CLK synchronous burst mode cycles for initial access shown IACC t ACC t OE Starting at an Odd Address Am42BDS640AG t CEZ BDH t BACC OEZ t RACC t ...
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... Min Min Min Max Read Min Toggle and Min Data# Polling Max Min OEH t CE Valid RD t ACC CAS AAVDH t AVDP t AAVDS Am42BDS640AG D8, D9 C8, C9 (54 MHz) (40 MHz) Unit 13 10 ...
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... AC CHARACTERISTICS CE#f OE# WE# DQ15-DQ0 A21-A0 AVD# Note Read Address Read Data OEH ACC RA Figure 19. Asynchronous Mode Read Am42BDS640AG t OEZ Valid RD November 1, 2002 ...
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... November 1, 2002 Description Readyw Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 20. Reset Timings Am42BDS640AG All Speed Options Unit Max 35 s Max 500 ns Min 500 ns Min 200 ns Min ...
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... AVD# or the active edge of CLK. 3. See the “Flash Erase And Programming Performance” section for more information. 4. Does not include the preprogramming time Synchronous Asynchronous Synchronous Asynchronous Am42BDS640AG All Speed Options Unit Min Min ...
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... WPH CLK can be either V 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. 6. AVD# must toggle during command sequence if CLK Am42BDS640AG Read Status Data Complete Progress t WHWH1 ...
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... WPH CLK can be either V 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. 6. AVD# must toggle during command sequence if CLK Am42BDS640AG Read Status Data Complete Progress t WHWH1 ...
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... The Synchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. 7. CLK must not have an active edge while WE AVD# must toggle during command sequence unlock cy- cles. Am42BDS640AG Read Status Data Complete Progress ...
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... The Synchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. 7. AVD# must toggle during command sequence unlock cy- cles ns CLK must not have an active edge while WE Am42BDS640AG Read Status Data Complete Progress t WHWH1 ...
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... Address bits A21–A12 are don’t cares during unlock cycles in the command sequence. November 1, 2002 555h for 10h for chip erase chip erase 30h WPH t WC Am42BDS640AG Read Status Data Complete Progress t WHWH2 55 ...
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... Data Don't Care OE ACC Note: Use setup and hold times from conventional program operation. Figure 26. Accelerated Unlock Bypass Programming Timing A0h Don't Care t VIDS t VID Am42BDS640AG PD Don't Care November 1, 2002 ...
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... Figure 28. Toggle Bit Timings (During Embedded Algorithm) November 1, 2002 CEZ t OEZ VA Status Data 3. AVD# must toggle between data reads. VA Status Data 3. AVD# must toggle between data reads. Am42BDS640AG Status Data t CEZ t OEZ Status Data 57 ...
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... V A Status Data 3. RDY is active with data (A18 = 0 in the Burst Mode Configuration Register). When A18 = 1 in the Burst Mode Configuration Register, RDY is active one clock cycle before data. 4. AVD# must toggle between data reads. Am42BDS640AG t IACC Status Data November 1, 2002 ...
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... Figure 30. Latency with Boundary Crossing November 1, 2002 C62 C63 C63 C63 RACC RACC latency t t RACC RACC latency D62 D63 Am42BDS640AG C64 C65 C66 C67 D64 D65 D66 D67 59 ...
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... Figure 31. Latency with Boundary Crossing C62 C63 C63 C63 RACC RACC latency t t RACC RACC latency D62 D63 into Program/Erase Bank Am42BDS640AG C64 40 Invalid Read Status November 1, 2002 ...
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... Figure 32. Example of Wait States Insertion (Standard Handshaking Device) November 1, 2002 total number of clock cycles following AVD# falling edge number of clock cycles programmed Am42BDS640AG D0 D1 Rising edge of next clock cycle following last wait state triggers next burst data ...
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... Read status (at least two cycles) in same bank and/or array data from other bank OEH t OEZ t ACC t t OEH SR Am42BDS640AG Begin another write or program command sequence GHWL RD AAh 555h November 1, 2002 ...
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... Address Data Out Previous Data Valid Note: CE1 CE2s = WE Figure 34. SRAM Read Cycle—Address Controlled November 1, 2002 UB#s and/or LB Am42BDS640AG D8, D9 C8, C9 Unit (54 MHz) (40 MHz) Min Max Max ...
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... CO1 t CO2 OLZ t BLZ t LZ Data Valid Figure 35. SRAM Read Cycle (Max.) is less than t (Min.) both for a given device and from device to device HZ LZ Am42BDS640AG BHZ t OHZ November 1, 2002 ...
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... WP (See Note (See Note 4) High-Z t WHZ applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am42BDS640AG D8, D9 C8, C9 Unit (54 MHz) (40 MHz) Min 70 85 Min 60 70 ...
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... (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am42BDS640AG t (See Note Data Valid High-Z is measured from the beginning of write ...
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... AS t (See Note 4) WP (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am42BDS640AG t (See Note Data Valid High-Z is measured from the beginning of write ...
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... V, one pin at a time. CC Test Setup OUT Test Conditions Am42BDS640AG Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec µs µs Excludes system level overhead (Note 5) sec sec , 1,000,000 cycles. Additionally, CC Min Max – ...
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... Test Setup CS1#s V – 0.2 V (Note 1.2 V, CE1#s V – 0 (Note 1) See data retention waveforms 0.2 V (CE2s controlled). Data Retention Mode t SDR CE1 0 Data Retention Mode t SDR CE2s < 0.2 V Am42BDS640AG Min Typ Max Unit 1.0 2.2 V 1.0 8 µA (Note RDR t RDR 69 ...
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... OUTER ROW 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTION OR OTHER MEANS. Am42BDS640AG ...
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... AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. November 1, 2002 Am42BDS640AG 71 ...