hi-3599pst Holt Integrated Circuits, Inc., hi-3599pst Datasheet - Page 6

• Manufacturer Part Number: hi-3599pst
• Description: Octal Arinc 429 Receivers With Label Recognition And Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
RECEIVER PARITY
If enabled by setting Control Register CR4 bit to ”1”, the receiver
parity circuit counts Ones received, including the parity bit. If the
result is odd, then a "0" appears in the 32nd bit.
Setting Control Register CR4 bit to ”0” disables parity checking
and all 32 bits are treated as data.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending on the state of Control
Register bits CR2, CR6, CR7 and CR8, the received 32-bit ARINC
word is then checked for correct decoding and label match before
it is loaded into the 4 x 32 Receive FIFO. ARINC words that do not
match required 9th and 10th ARINC bit and do not have a label
match are ignored and are not loaded into the Receive FIFO. The
adjacent table describes this operation.
CONTROL BITS
CR2, CR6-8
FLAG
ZEROS
ONES
NULL
CONTROL
LOAD
FIFO
EOS
Memory
16-label
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
SCK
CS
SO
SI
/
COMPARE
DECODE
LABEL /
FIGURE 2.
32 BIT SHIFT REGISTER
4 words X 32 bit
SPI INTERFACE
HOLT INTEGRATED CIRCUITS
FIFO
HI-3598, HI-3599
RECEIVER BLOCK DIAGRAM
WORD GAP
6
BIT CLOCK
CR2
DATA
START
0
1
1
0
0
1
1
1
1
PARITY
CHECK
ARINC word
WORD GAP
SEQUENCE
DETECTION
matches
Enabled
CONTROL
TABLE 3. FIFO LOADING CONTROL
ERROR
TIMER
label
Yes
Yes
Yes
No
No
No
X
X
X
32ND
BIT
END
ERROR
CLOCK
CR6
SEQUENCE
BIT CLOCK
COUNTER
END OF
0
0
0
1
1
1
1
1
1
AND
BIT
ARINC word
bits 10, 9
CR7, 8
match
Yes
Yes
Yes
No
No
No
X
X
X
Ignore data
Ignore data
Ignore data
Ignore data
Ignore data
Load FIFO
Load FIFO
Load FIFO
Load FIFO
ACLK
FIFO