am85c30 Advanced Micro Devices, am85c30 Datasheet - Page 27

• Manufacturer Part Number: am85c30
• Description: Enhanced Serial Communications Controller
• Manufacturer: Advanced Micro Devices

Enable
The byte counter is enabled when the SCC is in the
SDLC/HDLC mode and WR15 bit 2 is set to 1.
Reset
The byte counter is reset whenever an SDLC flag char-
acter is received. The reset is timed so that the contents
of the byte counter are successfully written into the
FIFO.
Increment
The byte counter is incremented by writes to the data
FIFO. The counter represents the number of bytes re-
ceived by the SCC, rather than the number of bytes
transferred from the SCC. (These counts may differ by
up to the number of bytes in the receive data FIFO con-
tained in the SCC.)
Am85C30 SDLC/HDLC Enhancement
Register Access
SDLC/HDLC enhancements on the Am85C30 are en-
abled or disabled via bits D
mines whether or not the 10
frame status FIFO is enabled while bit D
whether or not other enhancements are enabled via
= No Change From NMOS SCC DFN
RR7
RR6
RR15
FOY FDA
7
BC
7
7
7
BC
6
6
6
6
BC
BC
13
5
5
5
5
2
or D
12
BC
BC
FIFO Overflow Status
1 = FIFO Overflowed During Operation
0 = Normal
4
FIFO Data Available Status
1 = Status Reads Will Come From FIFO
0 = Status Reads Will Come From SCC
4
4
4
0
in WR15. Bit D
11
BC
BC
19 bit SDLC/HDLC
3
3
3
3
Figure 15. SCC Additional Registers
BC
BC
FEN
10
2
2
2
2
0
determines
BC
9
BC
2
1
1
1
1
deter-
BC
Am85C30
8
BC
Status FIFO Enable Control Bit
1 = Status and Byte Count Will be
0 = Status Will Not be Held (SCC Emulation Mode)
ENH
0
0
0
0
Held in the Status FIFO Until Read
Read From FIFO
LSB Byte Count
WR7 . Table 3 shows what functions on the Am85C30
are enabled when these bits are set.
When bit D
(RR6 and RR7) per channel specific to the 10
Frame Status FIFO are made available. The Am85C30
register map when this function is enabled is shown in
Table 4.
Bit D
hancements pertinent only to SDLC/HDLC mode opera-
tion are available for programming via WR7 as shown
below. Write Register 7 prime (WR7 ) can be written to
when bit D
ing to WR7 (flag register) actually writes to WR7 . If bit
D
isters WR3, WR4, WR5, and WR10 are readable by the
pro-cessor. In addition, WR7 is also readable by having
this bit set. WR3 is read when a bogus RR9 register is
accessed during a read cycle. WR10 is read by access-
ing RR11, and WR7 is accessed by executing a read to
RR14. The Am85C30 register map with bit D
and bit D
If both bits D
WR7 is set to 1, then the Am85C30 register map is as
shown in Table 6.
6
of this register is set to 1, previously unreadable reg-
ENH: SDLC/HDLC Enhancement Status
1 = Enhancements Enabled
0 = Enhancements Disabled
0
of WR15 determines whether or not other en-
6
0
of WR7 set is shown in Table 5.
2
of WR15 is set to 1. When this bit is set, writ-
of WR15 is set to 1, two additional registers
0
and D
2
of WR15 are set to 1 and D
10216F-19
AMD
0
of WR15
19 bit
6
27
of