am85c30 Advanced Micro Devices, am85c30 Datasheet - Page 23

• Manufacturer Part Number: am85c30
• Description: Enhanced Serial Communications Controller
• Manufacturer: Advanced Micro Devices

Am85C30 Timing
The ESCC generates internal control signals from WR
and RD that are related to PCLK. Since PCLK has no
phase relationship with WR and RD, the circuitry gener-
ating these internal control signals must provide time for
metastable conditions to disappear. This gives rise to a
recovery time related to PCLK. The recovery time ap-
plies only between bus transactions involving the
ESCC. The recovery time required for proper operation
is specified from the falling edge of WR or RD in the first
transaction involving the ESCC, to the falling edge of
WR or RD in the second transaction involving the
ESCC. This time must be at least 3 1/2 PCLK regardless
of which register or channel is being accessed.
D
D
0
0
0
0
1
1
1
1
7
7
D
D
0
0
1
1
0
0
1
1
6
0
0
1
1
6
D
Write Register 14
0
1
0
1
0
1
0
1
D
5
Write Register 10
0
1
0
1
5
D
D
Null Command
Enter Search Mode
Reset Missing Clock
Disable DPLL
Set Source = BR Generator
Set Source = RTxC
Set FM Mode
Set NRZI Mode
4
NRZ
NRZI
FM1 (Transition = 1)
FM0 (Transition = 0)
4
D
D
3
3
D
D
2
2
D
D
1
1
D
D
0
0
BR Generator Enable
BR Generator Source
DTR/Request Function
Auto Echo
Local Loopback
CRC Preset ‘1’ or ‘0’
6-Bit/8-Bit Sync
Loop Mode
Abort/Flag on Underrun
Mark/Flag Idle
Go Active on Roll
Figure 9. Write Register Bit Functions (continued)
D
7
D
6
D
Write Register 13
5
D
4
D
3
Am85C30
D
D
2
7
* Added Enhancement
D
D
1
6
D
D
Read Cycle Timing
Figure 10 illustrates Read cycle timing. Addresses on
A/B and D/C and the status on INTACK must remain sta-
ble throughout the cycle. If CE falls after RD falls or if it
rises before RD rises, the effective RD is shortened.
Write Cycle Timing
Figure 11 illustrates Write cycle timing. Addresses on
A/B and D/C and the status on INTACK must remain
stable throughout the cycle. If CE falls after WR falls or if
it rises before WR rises, the effective WR is shortened.
Data must be valid before the rising edge of WR.
D
7
0
Write Register 15
5
D
D
TC
TC
TC
TC
TC
TC
TC
TC
6
4
D
Write Register 12
8
9
10
11
12
13
14
15
D
5
3
D
D
4
Time Constant
2
Upper Byte of
D
D
3
1
D
D
2
0
D
1
SDLC/HDLC Enhancements Enable*
Zero Count IE
10
DCD IE
Sync/Hunt IE
CTS IE
Tx Underrun/EOM IE
Break/Abort IE
D
0
19 Bit FIFO Enable*
TC
TC
TC
TC
TC
TC
TC
TC
0
1
2
3
4
5
6
7
Time Constant
Lower Byte of
AMD
10216F-13
(concluded)
23