trcv012g5 ETC-unknow, trcv012g5 Datasheet - Page 12

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trcv012g5

Manufacturer Part Number
trcv012g5
Description
Trcv012g5 Gbits/s Trcv012g7 Gbits/s Gbits/s Limiting Amplifier, Clock Recovery, Data Demultiplexer
Manufacturer
ETC-unknow
Datasheet
TRCV012G5 and TRCV012G7
Preliminary Data Sheet
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
August 2000
Clock and Data Recovery (CDR)
(continued)
CDR Input Jitter Tolerance
The limiting amplifier plus CDR’s jitter tolerance performance meets the requirement shown in Figure 5 on page 13
when the limiting amplifier’s input signal is within the valid level range given in Table 9 on page 20, the loop filter in
Figure 4 is used, and the data sequence is a valid OC-48 SONET/SDH signal.
CDR Jitter Transfer
Using the loop filter in Figure 4, the CDR’s jitter transfer performance meets the requirement shown in Figure 6
when the input jitter magnitude is within the jitter tolerance requirements given in Figure 5 and the data sequence is
a valid OC-48 SONET/SDH signal. This specification applies to the jitter transferred from the limiting amplifier’s
input to the 2.5 Gbits/s recovered clock pins (CK2G5P/N).
12
Lucent Technologies Inc.

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