hi-8599 Holt Integrated Circuits, Inc., hi-8599 Datasheet - Page 4

• Manufacturer Part Number: hi-8599
• Description: Transmitter With Line Driver And Dual Receivers
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
RECEIVER LOGIC OPERATION
Figure 2 is a block diagram showing each receiver’s logic.
BIT TIMING
ARINC 429 specifies the following timing for received data:
The HI-8581 and HI-8589 accepts signals meeting these specifi-
cations and rejects signals outside these tolerances using the
method described here:
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
1. The timing logic requires an accurate 1.0 MHz clock
source. Less than 0.1% error is recommended.
2. The sampling shift registers are 10 bits long and must
show three consecutive Ones, Zeros or Nulls to be consid-
ered valid data. To qualify data bits, One or Zero in the upper
bits of the sampling shift register must be followed by Null in
the lower bits within the data bit time. A word gap Null re-
quires three consecutive Nulls in both the upper and lower
bits of the sampling shift register. This guarantees the mini-
mum pulse width.
3. Each data bit must follow its predecessor by not less than
8 samples and not more than 12 samples. In this manner the
DECODER
CONTROL
BITS
SEL
D/R
EN
ZEROS
ONES
NULL
/
100K BPS ± 1%
HIGH SPEED
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
CONTROL
CONTROL
5 µsec ± 5%
ENABLE
LATCH
MUX
EOS
BITS 9 & 10
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
FIGURE 2.
12K -14.5K BPS
34.5 - 41.7 µsec
LOW SPEED
HOLT INTEGRATED CIRCUITS
10 ± 5 µsec
10 ± 5 µsec
32 BIT SHIFT REGISTER
32 TO 16 DRIVER
32 BIT LATCH
TO PINS
RECEIVER BLOCK DIAGRAM
HI-8599
4
WORD GAP
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the par-
ity bit, ARINC bit 32. If the result is odd, then "0" will appear in the
32nd bit.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then EOS clocks the data
ready flag flip flop to a "1",
data flag for a receiver remains low until after
from that receiver are retrieved. This is accomplished by first acti-
vating
and then activating
EN1
ceiver 2.
BIT CLOCK
DATA
START
bit rate is checked. With exactly 1 MHz input clock frequency,
the acceptable data bit rates are as follows:
DATA BIT RATE MIN
DATA BIT RATE MAX
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter
is incremented. A count of 3 enables the next reception.
retrieves data from receiver 1 and
EN
CONTROL
BIT BD14
PARITY
CHECK
with SEL, the byte selector, low to retrieve the first byte
WORD GAP
SEQUENCE
DETECTION
CONTROL
ERROR
TIMER
32ND
BIT
EN
EOS
END
with SEL high to retrieve the second byte.
ERROR
CLOCK
SEQUENCE
COUNTER
BIT CLOCK
END OF
OPTION
CLOCK
D/R1
AND
BIT
or
HIGH SPEED
125K BPS
D/R2
83K BPS
CLOCK
EN2
(or both) will go low. The
retrieves data from re-
both
CLK
LOW SPEED
10.4K BPS
15.6K BPS
ARINC bytes