emc2106 Standard Microsystems Corp., emc2106 Datasheet - Page 75
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emc2106
Manufacturer Part Number
emc2106
Description
Emc2106 Dual Rpm-based Linear Fan Controller With Hardware Thermal Shutdown
Manufacturer
Standard Microsystems Corp.
Datasheet
1.EMC2106.pdf
(107 pages)
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Manufacturer
Quantity
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Part Number:
emc2106-DZK-TR
Manufacturer:
SMSC
Quantity:
20 000
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Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown
Datasheet
SMSC EMC2106
46h
86h
6.28
0
0
1
1
R/W
R/W
R/W
2
0
0
The Fan Spin Up Configuration Register controls the settings of Spin Up Routine. The Fan Spin Up
Configuration Register is software locked.
Bit 7 - 6 - DRIVE_FAIL_CNTx[1:0] - Determines how many update cycles are used for the Drive Fail
detection function as shown in
the desired tach target.
Bit 5 - NOKICKx - Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of
the programmed spin up time before driving it at the programmed level.
Bits 4 - 2 - SPIN_LVL[2:0] - Determines the final drive level that is used by the Spin Up Routine as
shown in
Fan Spin Up Configuration Registers
1
‘0’ (default) - The Spin Up Routine will drive the fan driver to 100% for 1/4 of the programmed spin
up time before reverting to the programmed spin level.
‘1’ - The Spin Up Routine will not drive the fan driver to 100%. It will set the drive at the
programmed spin level for the entire duration of the programmed spin up time.
DRIVE_FAIL_CNT[1:0]
Fan 1 Spin Up
Fan 2 Spin up
Configuration
Configuration
REGISTER
Table
6.42.
SPIN_LVL[2:0]
0
1
0
1
Table 6.40 Fan Spin Up Configuration Registers
Table 6.41 DRIVE_FAIL_CNT[1:0] Bit Decode
DRIVE_FAIL
DRIVE_FAIL
_CNT1 [1:0]
_CNT2 [1:0]
B7
1
0
0
0
Table
Table 6.42 Spin Level
B6
DATASHEET
6.41. This circuitry determines whether the fan can be driven to
ICK1
ICK2
NOK
NOK
B5
75
Disabled - the Drive Fail detection circuitry is
disabled (default)
16 - the Drive Fail detection circuitry will count for 16
update periods
32 - the Drive Fail detection circuitry will count for 32
update periods
64 - the Drive Fail detection circuitry will count for 64
update periods
B4
0
0
1
SPIN_LVL[2:0]
SPIN_LVL[2:0]
NUMBER OF UPDATE PERIODS
B3
B2
SPIN UP DRIVE LEVEL
SPINUP_TIM
SPINUP_TIM
B1
E [1:0]
E [1:0]
Revision 1.74 (05-08-08)
30%
35%
B0
DEFAULT
0Dh
0Dh
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