at86rf211 ATMEL Corporation, at86rf211 Datasheet - Page 23

• Manufacturer Part Number: at86rf211
• Description: Fsk Transceiver For Ism Radio Applications
• Manufacturer: ATMEL Corporation

Figure 29. Write Chronogram: Complete Write Cycle in a 10 bits Register
Figure 30. Write Chronogram: Partial Write Cycle, Writing 2 bits
1942C–WIRE–06/02
S L E
S C K
S D A T A
A[3]
S L E
S C K
S D A T A
A[2]
•
A message is made of 3 fields:
Variable register length and partial read or write cycles are supported.
In case of partial read or write cycles, the first data (in or out) is always the MSB of the
register.
•
The address, R/W and data bits are clocked on the rising edge of SCK.
If the number of data bits is lower than the register capacity, the LSB bits keep their
former value allowing safe partial write. If the number of data bits is greater than the reg-
ister capacity, the extra bits are ignored.
The data is actually written into the register on the rising edge of SLE when the data
length is less or equal to the register length.
When trying to write more data than the register length, data field is written on the first
extra rising clock edge regarding register length.
The complete register of 10 bits is updated on a rising edge of SLE.
A[1]
A[3]
Register Interface Format
WRITE Mode (R/W = 1)
–
–
–
A[0]
address A[3:0]: 4 bits (MSB first)
R/W: read/write selection
data D[31:0]: up to 32 bits (MSB first)
A[3]
A[2]
ADDRESS
R / W
A[2]
A[1]
D[9]
A[1]
A[0]
D[8]
A[0]
D[7]
R / W
R/W
R/W
D[6]
D[31]
MSB
D[5]
D[30]
D[4]
DATA up to 32 bits (variable length)
D[3]
D[2]
D[nbit-1:0]
D[1]
D[0]
AT86RF211
LSB
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