tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 80

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

TFRA08C13 OCTAL T1/E1 Framer
Alarms and Performance Monitoring
Receive Line Pattern Monitor—Using Register FRM_SR7
The receive framer pattern monitor continuously monitors the received line, detects the following fixed framed pat-
terns, and indicates detection in register FRM_SR7 bit 6 and bit 7.
In DS1 mode, the received 193 bit frame must consist of 192 bits of pattern plus 1 bit of framing information. In
CEPT mode, the received 256 bit frame must consist of 248 bits of pattern plus 8 bits (TS0) of framing information.
No signaling, robbed bit in the case of T1 and TS16 signaling in the case of CEPT, may be present for successful
detection of these two test patterns.
To establish lock to the pattern, 256 sequential bits must be received without error. When lock to the pattern is
achieved, the appropriate bit of register FRM_SR7 is set to a 1. Once pattern lock is established, the monitor can
withstand up to 32 single bit errors per frame without a loss of lock. Lock will be lost if more than 32 errors occur
within a single frame. When such a condition occurs, the appropriate bit of register FRM_SR7 is deasserted. The
monitor then resumes scanning for pattern candidates.
Receive Line Pattern Detector—Using Register FRM_PR70
Framed or unframed patterns indicated in Table 35 may be detected using register FRM_PR70. Detection of the
selected test pattern is indicated when register FRM_SR7 bit 4 is set to 1. Selection of a framed or unframed test
pattern is made through FRM_PR70 bit 3. Bit errors in the received test pattern are indicated when register
FRM_SR7 bit 5 = 1. The bit errors are counted and reported in registers FRM_SR8 and FRM_SR9, which are nor-
mally the BPV counter registers. (In this test mode, the BPV counter registers do not count BPVs but count only bit
errors in the received test pattern.)
Table 35. Register FRM_PR70 Test Patterns
80
MARK (all ones AIS)
QRSS (2
2
63 (2
511 (2
511 (2
2047 (2
2047 (2
2
2
2
2
1:1 (alternating)
The pseudorandom test pattern as described by ITU Rec. O.151 and illustrated in Figure 30. Detection of the
pattern is indicated by register FRM_SR7 bit 6 = 1.
The quasi-random test pattern described in AT&T Technical Reference 62411[5] Appendix and illustrated in Fig-
ure 29. Detection of the pattern is indicated by register FRM_SR7 bit 7 = 1.
5
15
20
20
23
– 1
– 1
– 1
– 1
– 1
6
9
9
– 1)
11
11
– 1)
– 1) reversed
20
– 1)
– 1) reversed
– 1 with zero suppression)
Pattern
Bit 7 Bit 6 Bit 5 Bit 4
0
0
0
0
0
0
0
0
1
1
1
1
1
Register FRM_PR70
1
1
0
0
0
0
1
1
0
0
0
0
1
(continued)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000