mh2040 Music Semiconductors, Inc., mh2040 Datasheet - Page 6

• Manufacturer Part Number: mh2040
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

TCLK (JTAG Test Clock, Input)
The TCLK input is the Test Clock input. This pin is
internally pulled up.
TMS (JTAG Test Mode Select, Input)
The TMS input is the Test Mode Select input. This pin is
internally pulled up.
TDI (JTAG Test Data Input, Input)
The TDI input is the Test Data input. This pin is internally
pulled up.
TDO (JTAG Test Data Output, Output)
The TCLK output is the Test Data Output. This pin is
internally pulled up.
DQ21
DQ26
DQ30 DQ31
VCC
GND
VCC DQ28
/CS2
MH2040 top view
/AV
/W
HARRP - HLA Packaged Asynchronous Data Recognition-Recall Processors
/RESET
DQ17
DQ18
DQ19
DQ20
DQ22
DQ23
DQ24
DQ25
DQ27
DQ29
GND
/CS1
GND
/OE
/VB
/E
NC
Figure 4: MH 2040 High density Leadless Array (HLA) pinout
/TRST
DQ16
TCLK
GND
DQ15
DQ14
TMS
TDI
DQ13
TDO GND
DQ12
VCC
AC0
DQ11
AC1
DQ10
DQ9
AC2
AC3
DQ8
VCC
6
/TRST (JTAG Reset, Input)
The /TRST input is the Reset input, and serves to reset the
Test Access Port circuitry to its reset condition. This pin is
internally pulled up.
VDD, VSS (Positive Power Supply, Ground)
These pins are the main power supply connections to the
MH2040. VDD must be held at +3.3 Volts and ± 0.3 Volts
relative to the VSS pin, which is at 0 Volts, system
reference potential, for correct operation of the device.
Note: The TCLK, TMS, TDI, TDO, and /TRST lines are defined
in the IEEE Standard Test Access Port and Boundary-scan
Architecture IEEE Standard. 1149.1-1990 and IEEE Standard.
1149.1a-1993.
GND
AC4
DQ6
DQ7
AC6
AC5
DQ5
AC7
VCC
GND
DQ4
AC8
DQ3
AC9 AC10
AC11
DQ1
DQ2
DQ0
DSC
GND
AA11
AA10
GND
GND
VCC
GND
/MM
PA3
PA1
PA0
AA8
AA6
AA4
AA3
AA2
AA0
/MF
/MI
GND
VCC
PA2
AA9
AA7
AA5
AA1
/FF
/FI
Rev. 1.0