m36p0r9070e0zace Numonyx, m36p0r9070e0zace Datasheet - Page 9

• Manufacturer Part Number: m36p0r9070e0zace
• Description: 512 Mbit X16, Multiple Bank, Multi-level, Burst Flash Memory 128 Mbit Burst Psram, 1.8v Supply, Multi-chip Package
• Manufacturer: Numonyx

M36P0R9070E0
2
2.1
2.2
2.3
2.4
Signal descriptions
See
connected to this device.
Address inputs (A0-A24)
Addresses A0-A22 are common inputs for the Flash memory and PSRAM components.
Addresses A23 and A24 are inputs for Flash memory components only. The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus
Write operations they control the commands sent to the Command Interface of the internal
state machine. The Flash memory is accessed through the Chip Enable signal (E
through the Write Enable signal (W
Enable signal (E
E
Data input/output (DQ0-DQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or
input a command or the data to be programmed during a Bus Write operation.
For the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the
data to or from the upper part of the selected address when Upper Byte Enable (UB
driven Low. The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the
lower part of the selected address when Lower Byte Enable (LB
UB
Latch Enable (L)
The Latch Enable pin is common to the Flash memory and PSRAM components.
For details of how the Latch Enable signal behaves, please refer to the datasheets of the
respective memory components: M69KB128AB for the PSRAM and M58PR512J for the
Flash memory.
Clock (K)
The Clock input pin is common to the Flash memory and PSRAM components.
For details of how the Clock signal behaves, please refer to the datasheets of the respective
memory components: M69KB128AB for the PSRAM and M58PR512J for the Flash
memory.
F
Low, and E
P
and LB
Figure 1., Logic diagram
P
are disabled, the Data Inputs/ Outputs are high impedance.
P
must not be Low at the same time.
P
) and the Write Enable signal (W
and
Table 1., Signal
F
), while the PSRAM is accessed through the Chip
P
names, for a brief overview of the signals
).
P
) is driven Low. When both
Signal descriptions
F
) and
P
) is
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