m36p0r9070e0zace Numonyx, m36p0r9070e0zace Datasheet - Page 15

• Manufacturer Part Number: m36p0r9070e0zace
• Description: 512 Mbit X16, Multiple Bank, Multi-level, Burst Flash Memory 128 Mbit Burst Psram, 1.8v Supply, Multi-chip Package
• Manufacturer: Numonyx

M36P0R9070E0
Table 2.
1. X = Don't care, de-a = de-asserted, a = asserted, CR = Configuration Register.
2. The DPD
3. In the Flash memory the WAIT signal polarity is configured using the Set Configuration Register command.
4. If ECR15 is set to '0', the Flash memory cannot enter the Deep Power-Down mode, even if DPD
5. In the Flash memory L can be tied to V
6. Depends on G
7. ECR15 has to be set to ‘1’ for the Flash memory to enter Deep Power-Down.
8. A18 and A19 are used to select the BCR, RCR or DIDR registers.
9. BCR and RCR only.
10. Bit 4 of the Refresh Configuration Register must be set to ‘0’, bit 4 (BCR4) of the Bus Configuration Register must be set to
Bus Read
Bus Write
Address Latch
Output Disable V
Standby
Reset
Deep Power-
Down
Word Read
Lower Byte
Read
Upper Byte
Read
Word Write
Lower Byte
Write
Upper Byte
Write
Read CR (CR
Controlled
Method)
Program CR
(CR
Controlled)
No Operation
Deep Power-
Down
Standby
‘0’, and E has to be maintained High, V
Operation
(10)
F
signal polarity depends on the value of the ECR14 bit.
Main operating modes
(9)
F
.
Any Flash memory mode
V
V
The Flash memory must
V
V
V
E
X
IH
IH
IL
IL
IL
IL
F
V
V
V
G
X V
X
X
X
IH
IH
IL
F
be disabled
is allowed
W
V
V
V
X
X
X
IH
IH
IH
IL
F
RP
V
V
V
V
V
V
V
IH
IH
IH
IH
IH
IH
IL
F
IH
de-a
de-a
de-a
de-a
de-a
de-a
IH
DPD
, during Deep Power-Down mode.
a
if the valid address has been previously latched.
(2)
(1)
(7)
(4)
(4)
(4)
(4)
(4)
(4)
F
WAIT
Low-
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
(3)
Z
V
V
V
V
IL
IL
IL
L
X
X
X
X
X
IL
(5)
(5)
V
V
V
E
IL
IH
IH
P
W
V
V
V
V
X X
X X
X X
IL
IH
IH
IH
P
Any PSRAM mode is allowed
G
V
V
V
V
X V
X V
X V
X
PSRAM must be disabled
IL
IL
IL
IL
P
UB
V
V
V
V
X
X
X
X
IH
IH
IL
IL
IL
IL
IL
P
LB
V
V
V
V
V
V
V
X
X
X
X
IH
IH
IL
IL
IL
IL
IL
P
CR
V
V
V
V
V
V
V
V
V
X
IH
IL
IL
IL
IL
IL
IL
IL
IL
P
0(BCR)X1
00(RCR)1
A19 A18
(DIDR)
00(RCR)
10(BCR)
X
X
X
(8)
Functional description
F
Valid
Valid
Valid
Valid
Valid
Valid
is asserted.
X
X
X
(8)
BCR/
A20-
RCR
Data
A17
A22
A0-
X
X
X
X
Data Output or
Output
Output
High-Z
Invalid
DIDR Content
DQ0-
Valid
Valid
Input
Valid
Input
Valid
DQ7
Data Output
BCR/RCR/
Data Input
High-Z
High-Z
High-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
X
Output
High-Z
Output
Invalid
DQ15
DQ8-
(6)
Input
Input
Valid
Valid
Valid
Valid
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