s71pl129ja0 Meet Spansion Inc., s71pl129ja0 Datasheet - Page 18
![no-image](/images/no-image-200.jpg)
s71pl129ja0
Manufacturer Part Number
s71pl129ja0
Description
Stacked Multi-chip Product Mcp Flash Memory And Psram 128 Megabit 8m X 16-bit Cmos 3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory With 64/32/16 Megabit 4m/2m/1m X 16-bit Pseudo-static Ram
Manufacturer
Meet Spansion Inc.
Datasheet
1.S71PL129JA0.pdf
(149 pages)
- Current page: 18 of 149
- Download datasheet (3Mb)
Pin Description
Logic Symbol
18
Amax–A0
DQ15–DQ0
CE#
OE#
WE#
V
NC
RY/BY#
WP# / ACC
V
V
RESET#
CE1# , CE2#
Not es:
1.
SS
IO
CC
Amax = A21
max+1
=
=
=
=
=
=
=
=
=
=
=
=
=
CE#
OE#
Amax–A0
WE#
WP#/ACC
RESET#
V
A d v a n c e
Chip Power Supply
Address bus
16-bit data inputs/outputs/float
Chip Enable Inputs
Output Enable Input
Write Enable
Device Ground
Pin Not Connected Internally
Ready/Busy output and open drain.
When RY/BY#= V
read operations and commands. When RY/BY#=
V
algorithm or the device is executing a hardware
reset operation.
Write Protect/Acceleration Input.
When WP#/ACC= V
4K-word sectors are write protected regardless of
other sector protection configurations. When WP#/
ACC= V
DYB or PPB is programmed. When WP# / ACC= 12V ,
program and erase operations are accelerated.
Input/Output Buffer Power Supply 2.7 V to 3.6 V
(2.7 V to 3.6 V or 2.7 to 3.3 V)
Hardware Reset Pin
Chip Enable Inputs.
CE1# controls the 64Mb in Banks 1A and 1B. CE2#
controls the 64 Mb in Banks 2A and 2B.
IO
OL
(V
S29PL129J for MCP
, the device is either executing an embedded
CCQ
)
IH
, these sector are unprotected unless the
DQ15–DQ0
RY/ BY#
I n f o r m a t i o n
IH
, the device is ready to accept
IL
, the highest and lowest two
16
S29PL129J_MCP_00_A0 June 4, 2004
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