s71pl129ja0 Meet Spansion Inc., s71pl129ja0 Datasheet - Page 144

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s71pl129ja0

Manufacturer Part Number
s71pl129ja0
Description
Stacked Multi-chip Product Mcp Flash Memory And Psram 128 Megabit 8m X 16-bit Cmos 3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory With 64/32/16 Megabit 4m/2m/1m X 16-bit Pseudo-static Ram
Manufacturer
Meet Spansion Inc.
Datasheet
Notes:
1. This timing diagram assumes CE2=H.
2. Write address is valid from either CE1# or WE# of last falling edge.
Notes:
1. This timing diagram assumes CE2=H.
2. OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read sequence.
144
ADDRESS
ADDRESS
UB#, LB#
UB#, LB#
CE1#
CE1#
DQ
DQ
WE#
WE#
Read/Write Timings
OE#
OE#
READ DATA OUTPUT
READ DATA OUTPUT
t
t
CHAH
CHAH
Figure 66. Read / Write Timing #1-2 (CE1#/WE#/OE# Control)
t
t
CP
t
CP
t
OH
OH
t
t
t
t
CHZ
CHZ
OHCL
OHCL
Figure 65. Read/Write Timing #1-1 (CE1# Control)
t
t
AS
AS
WRITE ADDRESS
WRITE ADDRESS
A d v a n c e
t
t
CW
t
t
WC
WC
WP
WRITE DATA INPUT
pSRAM Type 7
WRITE DATA INPUT
t
DS
t
DS
t
t
t
WR
DH
I n f o r m a t i o n
WR
t
DH
t
t
CP
CP
t
t
ASC
ASC
t
CLZ
t
OLZ
READ ADDRESS
READ ADDRESS
t
t
CE
CE
t
pSRAM_Type07_13_A1 November 2, 2004
READ DATA OUTPUT
OE
t
t
RC
RC
t
t
t
OH
CHAH
CHAH
t
OH

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