89hpes12t3g2 Integrated Device Technology, 89hpes12t3g2 Datasheet - Page 2

• Manufacturer Part Number: 89hpes12t3g2
• Description: 12-lane, 3-port Gen2 Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

Product Description
provides the most efficient fan-out solution for applications requiring high
throughput, low latency, and simple board layout with a minimum
number of board layers. It provides 12 GBps (96 Gbps) of aggregated,
full-duplex switching capacity through 12 integrated serial lanes, using
proven and robust IDT technology. Each lane provides 5 Gbps of band-
width in both directions and is fully compliant with PCI Express Base
Specification, Revision 2.0.
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 2.0. The PES12T3G2 can operate either as a store and
forward or cut-through switch and is designed to switch memory and I/O
transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management to enable effi-
cient switching and I/O connectivity for servers, storage, and embedded
processors with limited connectivity.
IDT 89HPES12T3G2 Data Sheet
Utilizing standard PCI Express interconnect, the PES12T3G2
The PES12T3G2 is based on a flexible and efficient layered architec-
◆
◆
◆
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Spec-
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Packaged in a 19mm x 19mm 324-ball BGA with 1mm ball
spacing
Testability and Debug Features
Nine General Purpose Input/Output Pins
ification, Revision 2.0 (ACPI) supporting active link state
PCI Express
Figure 2 I/O Expansion Application
Slot
Processor
PES12T3G2
x4
x4
10GbE
I/O
x4
Bridge
North
Processor
10GbE
I/O
x4
SATA
I/O
Memory
Memory
Memory
Memory
2 of 31
SMBus Interface
face provides full access to the configuration registers in the
PES12T3G2, allowing every configuration register in the device to be
read or written by an external agent. The master interface allows the
default configuration register values of the PES12T3G2 to be over-
ridden following a reset with values programmed in an external serial
EEPROM. The master interface is also used by an external Hot-Plug I/O
expander.
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROM from which data is loaded to be config-
ured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
in a unified or split configuration. In the unified configuration, shown in
Figure 3(a), the master and slave SMBuses are tied together and the
PES12T3G2 acts both as a SMBus master as well as a SMBus slave on
this bus. This requires that the SMBus master or processor that has
access to PES12T3G2 registers supports SMBus arbitration. In some
systems, this SMBus master interface may be implemented using
general purpose I/O pins on a processor or micro controller, and may
not support SMBus arbitration. To support these systems, the
PES12T3G2 may be configured to operate in a split configuration as
shown in Figure 3(b).
two independent buses and thus multi-master arbitration is never
required. The PES12T3G2 supports reading and writing of the serial
EEPROM on the master SMBus via the slave SMBus, allowing in
system programming of the serial EEPROM.
The PES12T3G2 contains two SMBus interfaces. The slave inter-
Six pins make up each of the two SMBus interfaces. These pins
As shown in Figure 3, the master and slave SMBuses may be used
In the split configuration, the master and slave SMBuses operate as
Bit
Table 1 Master and Slave SMBus Address Assignment
1
2
3
4
5
6
7
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
SSMBADDR[5]
Address
SMBus
Slave
0
1
1
March 27, 2008
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
MSMBADDR[4]
Address
Master
SMBus
1
0
1