89hpes12n3 Integrated Device Technology, 89hpes12n3 Datasheet - Page 3

• Manufacturer Part Number: 89hpes12n3
• Description: 12-lane, 3-port Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

Pin Description
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES12N3 Data Sheet
The following tables list the functions of the pins provided on the PES12N3. Some of the functions listed may be multiplexed onto the same pin.
PEREFCLKP[1:0]
PEREFCLKN[1:0]
MSMBADDR[4:1]
PEARP[3:0]
PEARN[3:0]
PEBRP[3:0]
PEBRN[3:0]
PECRP[3:0]
PECRN[3:0]
PECTN[3:0]
PEATP[3:0]
PEATN[3:0]
PEBTP[3:0]
PEBTN[3:0]
PECTP[3:0]
MSMBDAT
MSMBCLK
REFCLKM
PEALREV
PEBLREV
PECLREV
Signal
Signal
Type
Type
I/O
I/O
O
O
O
I
I
I
I
I
I
I
I
I
Table 2 SMBus Interface Pins (Part 1 of 2)
PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port A are reversed. This value may be overridden by modify-
ing the value of the PALREV bit in the PA_SWCTL register.
PCI Express Port A Serial Data Receive. Differential PCI Express receive
pairs for port A.
PCI Express Port A Serial Data Transmit. Differential PCI Express trans-
mit pairs for port A
PCI Express Port B Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port B are reversed. This value may be overridden by modify-
ing the value of the PBLREV bit in the PA_SWCTL register.
PCI Express Port B Serial Data Receive. Differential PCI Express receive
pairs for port B.
PCI Express Port B Serial Data Transmit. Differential PCI Express trans-
mit pairs for port B
PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port C are reversed. This value may be overridden by modify-
ing the value of the PCLREV bit in the PA_SWCTL register.
PCI Express Port C Serial Data Receive. Differential PCI Express receive
pairs for port C.
PCI Express Port C Serial Data Transmit. Differential PCI Express trans-
mit pairs for port C
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select. These signals select the fre-
quency of the reference clock input.
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
Table 1 PCI Express Interface Pins
0x0 - 100 MHz
0x1 - 125 MHz
3 of 28
Name/Description
Name/Description
July 18, 2006