89hpes16nt2 Integrated Device Technology, 89hpes16nt2 Datasheet - Page 3

• Manufacturer Part Number: 89hpes16nt2
• Description: 16-lane, 2-port Pcie Inter-domain Switch
• Manufacturer: Integrated Device Technology

Pin Description
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES16NT2 Data Sheet
The following tables list the functions of the pins provided on the PES16NT2. Some of the functions listed may be multiplexed onto the same pin.
PEREFCLKN[1:0]
PEREFCLKP[1:0]
PECRN[7:0]
PEARP[7:0]
PEARN[7:0]
PEATN[7:0]
PECRP[7:0]
PECTP[7:0]
PECTN[7:0]
PEATP[7:0]
REFCLKM
PEALREV
PECLREV
Signal
Figure 2 PCIe System Interconnect Architecture Block Diagram
PES16NT2
Embedded
Type
CPU
CPU
FC
O
O
I
I
I
I
I
I
PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port A are reversed. This value may be overridden by modify-
ing the value of the PALREV bit in the PA_SWCTL register.
PCI Express Port A Serial Data Receive. Differential PCI Express receive
pairs for port A.
PCI Express Port A Serial Data Transmit. Differential PCI Express trans-
mit pairs for port A
PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port C are reversed. This value may be overridden by modify-
ing the value of the PCLREV bit in the PA_SWCTL register.
PCI Express Port C Serial Data Receive. Differential PCI Express receive
pairs for port C.
PCI Express Port C Serial Data Transmit. Differential PCI Express trans-
mit pairs for port C
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select. These signals select the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 1 PCI Express Interface Pins
PCIe System Interconnect Switch
PES16NT2
CPU
SATA / SAS
Embedded
3 of 29
CPU
Name/Description
GbE / 10GigE
Embedded
PES16NT2
CPU
CPU
January 14, 2008