89hpes16t4bg2 Integrated Device Technology, 89hpes16t4bg2 Datasheet - Page 6

• Manufacturer Part Number: 89hpes16t4bg2
• Description: 16-lane 4-port Gen2 Pci Express Switch
• Manufacturer: Integrated Device Technology

© 2009 Integrated Device Technology, Inc
IDT 89HPES16T4BG2 Data Sheet
MSMBSMODE
SWMODE[2:0]
RSTHALT
Signal
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
Signal
CCLKDS
CCLKUS
PERSTN
*Notice: The information in this document is subject to change without notice
Type
Type
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
Table 4 General Purpose I/O Pins (Part 2 of 2)
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P6RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 6.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be overridden by modifying the SCLK bit in each down-
stream port’s PCIELSTS register.
Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the P0_PCIELSTS register.
Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
Fundamental Reset. Assertion of this signal resets all logic inside
PES16T4BG2 and initiates a PCI Express fundamental reset.
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES16T4BG2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
Switch Mode. These configuration pins determine the PES16T4BG2
switch operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0x7 Reserved
These pins should be static and not change following the negation of
PERSTN.
Table 5 System Pins
6 of 32
Name/Description
Name/Description
July 1, 2009