89hpes16t4bg2 Integrated Device Technology, 89hpes16t4bg2 Datasheet - Page 2

• Manufacturer Part Number: 89hpes16t4bg2
• Description: 16-lane 4-port Gen2 Pci Express Switch
• Manufacturer: Integrated Device Technology

Product Description
provides the most efficient fan-out solution for applications requiring high
throughput, low latency, and simple board layout with a minimum
number of board layers. It provides 16 GBps (128 Gbps) of aggregated,
full-duplex switching capacity through 16 integrated serial lanes, using
proven and robust IDT technology. Each lane provides 5 Gbps of band-
width in both directions and is fully compliant with PCI Express Base
Specification, Revision 2.0.
tecture. The PCI Express layer consists of SerDes, Physical, Data Link
and Transaction layers in compliance with PCI Express Base specifica-
tion Revision 2.0. The PES16T4BG2 can operate either as a store and
forward or cut-through switch and is designed to switch memory and I/O
transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management to enable effi-
cient switching and I/O connectivity for servers, storage, and embedded
processors with limited connectivity.
© 2009 Integrated Device Technology, Inc
Utilizing standard PCI Express interconnect, the PES16T4BG2
The PES16T4BG2 is based on a flexible and efficient layered archi-
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IDT 89HPES16T4BG2 Data Sheet
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– Internal end-to-end parity protection on all TLPs ensures data
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
– Supports Hot-Swap
– Utilizes advanced low-power design techniques to achieve low
– Support PCI Express Power Management Interface specifica-
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Spec-
– Supports IEEE 1149.1 JTAG and IEEE 1149.6 AC JTAG
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Packaged in a 23mm x 23mm, 288-ball BGA with 1mm
ball spacing
Reliability, Availability, and Serviceability (RAS) Features
Power Management
Testability and Debug Features
Sixteen General Purpose Input/Output Pins
integrity even in systems that do not implement end-to-end
CRC (ECRC)
boards
typical power consumption
tion (PCI-PM 2.0)
ification, Revision 2.0 (ACPI) supporting active link state
*Notice: The information in this document is subject to change without notice
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SMBus Interface
face provides full access to the configuration registers in the
PES16T4BG2, allowing every configuration register in the device to be
read or written by an external agent. The master interface allows the
default configuration register values of the PES16T4BG2 to be over-
ridden following a reset with values programmed in an external serial
EEPROM. The master interface is also used by an external Hot-Plug I/O
expander.
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROM from which data is loaded to be config-
ured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
The PES16T4BG2 contains two SMBus interfaces. The slave inter-
Six pins make up each of the two SMBus interfaces. These pins
Bit
Table 1 Master and Slave SMBus Address Assignment
1
2
3
4
5
6
7
PCI Express
Figure 2 I/O Expansion Application
Slot
PES16T4BG2
Processor
x4
x4
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
SSMBADDR[5]
10GbE
Address
I/O
SMBus
x4
Slave
Bridge
North
0
1
1
Processor
10GbE
I/O
x4
SATA
I/O
Memory
Memory
Memory
Memory
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
MSMBADDR[4]
Address
Master
SMBus
SATA
I/O
1
0
1
July 1, 2009