zl50073 Zarlink Semiconductor, zl50073 Datasheet - Page 37

• Manufacturer Part Number: zl50073
• Description: 32 K Channel Digital Switch With High Jitter Tolerance, Rate Conversion Per Group Of 4 Streams 8, 16, 32 Or 64 Mbps
• Manufacturer: Zarlink Semiconductor

14.1.2
The Connection Memory Least Significant Byte field is provided to give a convenient alternative way to modify the
output data for a stream in message mode. In this memory address range, all of the connection memory least
significant bytes (bits 7 - 0) are available for read/write in consecutive address locations. This feature is provided for
programming convenience. It can allow higher programming bandwidth on message mode streams. For example,
one longword access to this memory space can read or set the message bytes in four consecutive connection
memory locations. Access to this memory space is big-endian, with the most significant bytes on the data bus
accessing the lower address of the connection memory. For example, for 32-bit data bus, to access the Connection
Memory LSB associated with channels 3 - 0 on a particular stream, the data bus D31 - 24 carry data for channel 0,
D23 - 16 carry data for channel 1, D15 - 8 carry data for channel 2, and D7 - 0 carry data for channel 3. Addressing
into each of the streams is illustrated in Table 17.
PCF
9 - 0
External Read/Write Address: 000000
Reset Value: 0000
31
15
Bit
2
0
PCF
GP
30
14
1
4
Connection Memory LSB
Output
Group
0
1
2
3
4
5
Name
STCH
9 - 0
PCF
GP
29
13
0
3
H
Address
V/D
GP
28
12
020C00
020000
020400
020800
021000
021400
Table 17 - Connection Memory LSB Group Address Mapping
2
Source Stream and Channel Selection / Message Mode Data
In connection mode (constant/variable delay), these bits define the input/source stream
and channel number, depending on the data rate.
For 65.536 Mbps, bits 9 - 0 select the input channel (0 - 1023).
For 32.768 Mbps, bits 9 - 1 select the input channel (0 - 511). Bit 0 selects stream STiA
(0) or STiB (1).
For 16.869 Mbps, bits 9 - 2 select the input channel (0 - 255). Bits 1 - 0 select stream
STiA (00), STiB (01), STiC (10), or STiD (11).
For 8.192 Mbps, bits 9 - 3 select the input channel (0 - 127). Bit 2 MUST be set to 0. Bits
1 - 0 select stream STiA (00), STiB (01), STiC (10), or STiD (11).
In message mode, bits 7 - 0 define the output data. The data is output sequentially with
bit 7 being output first. Bits 9 - 8 are not used.
(Hex)
Start
Table 16 - Connection Memory Bits (CMB) (continued)
ICL
GP
27
11
1
1
H
ICL
GP
26
10
020C00 - 020FFF
0
0
020000 - 0203FF
020400 - 0207FF
020800 - 020BFF
021000 - 0213FF
021400 - 0217FF
Address Range
STCH
OCL
(Hex)
25
1
9
9
Zarlink Semiconductor Inc.
STCH
OCL
ZL50073
24
8
0
8
37
STCH
23
Output
0
7
7
Group
16
17
18
19
20
21
Description
STCH
22
6
0
6
Address
STCH
024C00
024000
024400
024800
025000
025400
21
(Hex)
5
0
5
Start
STCH
20
0
4
4
024C00 - 024FFF
024800 - 024BFF
STCH
024000 - 0243FF
024400 - 0247FF
025000 - 0253FF
025400 - 0257FF
Address Range
19
0
3
3
(Hex)
STCH
18
2
0
2
Data Sheet
STCH
17
0
1
1
STCH
16
0
0
0