zl50058 Zarlink Semiconductor, zl50058 Datasheet - Page 41
zl50058
Manufacturer Part Number
zl50058
Description
12 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 48 Input And 48 Output Streams
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50058.pdf
(108 pages)
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Figure 14, Local Port External High Impedance Control Timing (32 Mbps Mode) shows the channel control bits for
LCSTo0 and LCSTo1.
4.3
When the LORS input pin is HIGH, the Local Output Enable Bit (LE) of the Local Connection Memory has direct
per-channel control on the high impedance state of the Local output streams, LSTo0-15. Programming a LOW state
in the connection memory LE bit will set the stream output of the device to high impedance for the duration of the
channel period. See “Local Connection Memory Bit Definition,” on page 60 for programming details.
When the LORS signal is asserted HIGH, the LCSTo0-1 outputs directly the values given in LE.
LORS Asserted HIGH
(32 Mbps)
(3 2Mbps)
(32 Mbps)
(32 Mbs)
LCSTo0
LCSTo1
LSTo0
LSTo3
LSTo2
LSTo1
FP8o
C8o
Figure 14 - Local Port External High Impedance Control Timing (32 Mbps Mode)
Channel 0
bits 7-0
Channel 0
bits 7-0
Channel 0
bits 7-0
Channel 0
bits 7-0
Zarlink Semiconductor Inc.
Channel 1
bits 7-0
Channel 1
bits 7-0
Channel 1
bits 7-0
Channel 1
bits 7-0
ZL50057/8
41
Channel 510
bits 7-0
Channel 510
bits 7-0
Channel 510
bits 7-0
Channel 510
bits 7-0
One C16o cycle
Channel 511
bits 7-0
Channel 511
bits 7-0
Channel 511
bits 7-0
Channel 511
bits 7-0
Data Sheet
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