zl50058 Zarlink Semiconductor, zl50058 Datasheet - Page 13
zl50058
Manufacturer Part Number
zl50058
Description
12 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 48 Input And 48 Output Streams
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50058.pdf
(108 pages)
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Pin Description (continued)
Backplane and Local Outputs and Control
Pin Name
LSTi8-15
LSTi0-7
ODE
Coordinates
M18, M19,
L20, M17,
N19, N20,
P20, R18,
M20, N18
P17, P19,
L18, L19,
R19, R20
Package
(272-ball
ZL50057
PBGA)
A12
Coordinates
M13, M14,
M15, M16,
N12, N13,
K13, K14,
K15, K16,
L13, L14,
N14, N15
Package
(256-ball
ZL50058
L15, L16
PBGA)
B10
Zarlink Semiconductor Inc.
ZL50057/8
Local Serial Input Streams 0 to 7 (5 V Tolerant Inputs with
Internal Pull-downs).
In Local Non-32 Mbps Mode, these pins accept serial TDM
data streams at a data rate of:
16.384 Mbps (with 256 channels per stream),
8.192 Mbps (with 128 channels per stream),
4.096 Mbps (with 64 channels per stream) or
2.048 Mbps (with 32 channels per stream).
The data rate is independently programmable for each input
stream.
In Local 32 Mbps Mode, these pins accept serial TDM data
streams at a fixed data rate of 32.768 Mbps (with 512
channels per stream).
Local Serial Input Streams 8 to 15 (5 V Tolerant Inputs
with Internal Pull-downs).
In Local Non-32 Mbps Mode, these pins accept serial TDM
data streams at a data rate of:
16.384 Mbps (with 256 channels per stream),
8.192 Mbps (with 128 channels per stream),
4.096 Mbps (with 64 channels per stream) or
2.048 Mbps (with 32 channels per stream).
The data rate is independently programmable for each input
stream.
In Local 32 Mbps Mode, these pins are unused and should be
externally connected to a defined logic level.
Output Drive Enable (5 V Tolerant Input with Internal
Pull-up).
An asynchronous input providing Output Enable control to the
BSTo0-31, LSTo0-15, BCSTo0-3, and LCSTo0-1 outputs.
When LOW, the BSTo0-31 and LSTo0-15 outputs are driven
HIGH or high impedance (dependent on the BORS and LORS
pin settings respectively) and the outputs BCSTo0-3 and
LCSTo0-1 are driven low.
When HIGH, the outputs BSTo0-31, LSTo0-15, BCSTo0-3,
and LCSTo0-1 are enabled.
13
Description
Data Sheet
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