mt90226ag ETC-unknow, mt90226ag Datasheet - Page 51

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
15:14
Bit #
Bit #
1:0
15
14
13
13
12
11
10
a. Unassigned Cells have a fixed header corresponding to 00000000 00000000 00000000 0000xxx0.
b. Idle Cells have a fixed header corresponding to 00000000 00000000 00000000 00000001
9
8
7
6
5
4
3
2
Type
Type
ROL
ROL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
Unused. Read all 0’s
Reserved.
Parity Bit. The incoming Parity Bit is odd parity when 0, even parity when 1.
Reserved. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
UTOPIA loopback mode indicator. When set the Tx UTOPIA will accept cells and loop
these back to the Rx UTOPIA interface. The Rx UTOPIA interface will then output these
cells.
Reserved. Write 0 for normal operation.
Selects between 16- and 8-bit mode for the Utopia bus. A 0 selects a 16-bit wide bus and a
1 selects an 8-bit wide bus.
A 1 resets the state of the Input UTOPIA Controller. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
Unassigned Cell Filter. A 1 signifies that the Unassigned
will be discarded. The Unassigned/Idle cell counter is incremented for each cell discarded.
Idle Cell Filter. A 1 signifies that the Idle
discarded. The Unassigned/Idle cell counter is incremented for each cell discarded.
ATM Forum Polynomial. A 1 disables the addition of the ATM Forum Polynomial calculation
on the HEC calculated as per I.432. A 0 means that the coset value is included in the HEC
value.
HEC Verification.
11: Enable HEC error correction if 1 bit is wrong, discard cell if more than 1 bit are wrong.
10: Discard cell if HEC is wrong, no HEC correction.
01: Enable HEC error correction if 1 bit is wrong, no correction if more than 1 bit wrong, cell
is not discarded if HEC is wrong.
00: No verification of HEC.
Indicates that the parity error counter has rolled-over. This is a sticky bit which is set by
the hardware and reset by the user (by writing ’0’ to this bit).
Indicates that at least one parity error has occurred since this register was reset. This is a
sticky bit which is set by the hardware and reset by the user (by writing ’0’ to this bit.
When written with a 1 the internal TX UTOPIA Parity Error Counter value will be
transferred to the lower 12 bits of this register. When written with ’0’, no transfer is done.
0x0052 (1 reg)
1 register for all the UTOPIA Input ports.
000X000000000000
0x0053 (1 reg)
1 register to contain information about parity errors on the Tx UTOPIA data bus.
0000
Table 10 - UTOPIA Input Parity Error Register
Table 9 - UTOPIA Input Control Register
Zarlink Semiconductor Inc.
Description
Description
b
cells coming from the ATM layer will be
a
cells coming from the ATM layer
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