mt90226ag ETC-unknow, mt90226ag Datasheet - Page 3

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
1.0 Device Architecture ......................................................................................................... 22
2.0 The ATM Transmit Path................................................................................................... 23
3.0 The ATM Receive Path .................................................................................................... 26
4.0 Description of the TDM Interface.................................................................................... 29
5.0 UTOPIA Interface Operation ........................................................................................... 39
6.0 Support Blocks ................................................................................................................ 43
1.1 MT90225/6 Main Functions ...................................................................................................................... 22
2.1 Cell In Control ........................................................................................................................................... 23
2.2 The ATM Transmission Convergence ...................................................................................................... 24
2.3 Parallel to Serial TDM Interface ................................................................................................................ 25
3.1 Cell Delineation Function .......................................................................................................................... 26
3.2 De-Scrambling and ATM Cell Filtering...................................................................................................... 28
4.1 Single mode .............................................................................................................................................. 29
4.2 Wire-OR mode .......................................................................................................................................... 31
4.3 Multiplex mode .......................................................................................................................................... 32
4.4 Non-framed mode ..................................................................................................................................... 34
4.5 Clock formats ............................................................................................................................................ 35
4.6 TDM Loopback Mode................................................................................................................................ 35
4.7 Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters................................................................. 36
4.8 Clocking Options ....................................................................................................................................... 37
5.1 ATM Input Port.......................................................................................................................................... 39
5.2 ATM Output Port ....................................................................................................................................... 40
5.3 UTOPIA Operation .................................................................................................................................... 40
5.4 UTOPIA Operation With a Single PHY ..................................................................................................... 40
5.5 UTOPIA Operation with Multiple PHY....................................................................................................... 41
5.6 UTOPIA Loopback .................................................................................................................................... 41
5.7 Examples of UTOPIA Operation Modes ................................................................................................... 41
6.1 Counter Block ........................................................................................................................................... 43
6.2 Interrupt Block ........................................................................................................................................... 44
2.2.1 TX Cell RAM and TX Link FIFO Length .......................................................................................... 25
3.1.1 Cell Delineation with Sync signal..................................................................................................... 28
3.1.2 Cell Delineation without Sync signal................................................................................................ 28
4.1.1 Single mode - Generic 1.544MHz ................................................................................................... 29
4.1.2 Single mode - Generic 2.048MHz ................................................................................................... 30
4.1.3 Single mode -ST-BUS ..................................................................................................................... 31
4.2.1 Wire-OR mode - 2 link grouping ...................................................................................................... 32
4.2.2 Wire-OR mode - 4 link grouping ...................................................................................................... 32
4.3.1 Multiplex mode - 2 link multiplexing................................................................................................. 33
4.3.2 Multiplex mode - 4 link multiplexing................................................................................................. 33
4.4.1 Non-framed mode - 2.5Mbps........................................................................................................... 34
4.4.2 Non-framed mode - 5.0Mbps........................................................................................................... 34
4.4.3 Non-framed mode - 10.0Mbps......................................................................................................... 35
4.8.1 Verification of the RXSYNC Period ................................................................................................. 37
4.8.2 Verification of the TXSYNC Period.................................................................................................. 38
4.8.3 Primary and Secondary Reference Signals..................................................................................... 38
4.8.4 Verification of Clock Activity ............................................................................................................ 38
4.8.5 Clock Selection................................................................................................................................ 38
6.1.1 UTOPIA Input I/F counters .............................................................................................................. 43
6.1.2 Transmit TDM I/F Counters ............................................................................................................. 43
6.1.3 Receive TDM I/F Counters .............................................................................................................. 43
6.1.4 Access to the Counters ................................................................................................................... 43
6.1.5 Latching counter mode .................................................................................................................... 44
Zarlink Semiconductor Inc.
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