mt90823ap1 Zarlink Semiconductor, mt90823ap1 Datasheet - Page 20

• Manufacturer Part Number: mt90823ap1
• Description: 2048 X 2048 Channels Selectable Rate 2, 4, 8 Mbps 3.3 V Non-blocking Large Digital Switch Ldx
• Manufacturer: Zarlink Semiconductor

Note 1: n denotes an input stream number from 0 to 15.
OFn2, OFn1, OFn0
OF152
OF112
OF32
OF72
15
15
15
15
(Note 1)
Read/Write Address:
Reset value:
Name
DLEn
OF151
OF111
OF31
OF71
14
14
14
14
OF110
OF150
OF70
OF30
13
13
13
13
DLE11
DLE15
DLE7
DLE3
Offset Bits 2,1 & 0. These three bits define how long the serial interface receiver takes
to recognize and store bit 0 from the STi input pin: i.e., to start a new frame. The input
frame offset can be selected to +4 clock periods from the point where the external
frame pulse input signal is applied to the F0i input of the device. See Figure 4.
Data Latch Edge.
ST-BUS mode:DLEn =0, if clock rising edge is at the 3/4 point of the bit cell.
DLEn =1, if when clock falling edge is at the 3/4 of the bit cell.
GCI mode:DLEn =0, if clock falling edge is at the 3/4 point of the bit cell.
DLEn =1, if when clock rising edge is at the 3/4 of the bit cell.
12
12
12
12
Table 11 - Frame Input Offset (FOR) Register Bits
OF102
OF142
OF62
OF22
11
11
11
11
03
04
05
06
0000
H
H
H
H
OF101
OF141
OF21
OF61
10
10
10
10
for FOR0 register,
for FOR1 register,
for FOR2 register,
for FOR3 register,
H
for all FOR registers.
OF100
OF140
OF20
OF60
9
9
9
9
Zarlink Semiconductor Inc.
FOR0 register
FOR1 register
FOR2 register
FOR3 register
DLE10
DLE14
MT90823
DLE2
DLE6
8
8
8
8
20
OF52
OF92
OF132
OF12
7
7
7
7
Description
OF131
OF51
OF91
OF11
6
6
6
6
OF130
OF50
OF90
OF10
5
5
5
5
DLE13
DLE5
DLE9
DLE1
4
4
4
4
OF122
OF02
OF42
OF82
3
3
3
3
OF121
OF41
OF81
OF01
2
2
2
2
OF120
OF00
OF40
OF80
1
1
1
1
Data Sheet
DLE12
DLE4
DLE8
DLE0
0
0
0
0