zl30414 Zarlink Semiconductor, zl30414 Datasheet
zl30414
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zl30414 Summary of contents
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... Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. SONET/SDH Clock Multiplier PLL Ordering Information ZL30414QGC ZL30414QGC1 64 Pin TQFP* Trays Description The ZL30414 is an analog phase-locked loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET networking equipment. The ZL30414 generates very ...
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... GND ZL30414 EP_GND LPF ZL30414 Figure 2 - TQFP 64 pin (Top View) Description Ground. 0 volt Positive Analog Power Supply. +3.3 V ±10%. Positive Analog Power Supply. +3.3 V ±10%. C155 Clock Output (CML). These outputs provide a differential 155.52 MHz clock ...
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... GND 31 VDD 32 GND ZL30414 Description Bias. See Figure 13 for the recommended bias circuit. C155o Clock Enable (CMOS Input). If tied high this control pin enables the C155oP/N differential driver. Pulling this input low disables the output clock and deactivates differential drivers. C622 Clock Output Enable A (CMOS Input). If tied high this control pin enables the C622oP/N-A output clock ...
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... GND 57 VCC 58 C622oN-B 59 C622oP-B ZL30414 Description Ground. 0 volt Positive Digital Power Supply. +3.3 V ±10% C19 Clock Output (CMOS Output). This pin provides a single-ended CMOS clock at 19.44 MHz. Ground. 0 volt Lock Indicator (CMOS Output). This output goes high when PLL is frequency locked to the input reference C19i. ...
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... Functional Description The ZL30414 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-192/STM-64, OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30414 is shown in Figure 1 and a brief description is presented in the following sections. 1.1 Frequency/Phase Detector The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback signal from the Frequency Divider circuit and provides an error signal corresponding to the frequency/phase difference between the two ...
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... C622oP/N-D C155oP/N C19o To reduce power consumption and achieve the lowest possible intrinsic jitter the unused output clocks must be disabled. If any of the LVPECL outputs are disabled they must be left open without any terminations. ZL30414 Output Clocks Output Enable Pins C622oEN-A C622oEN-B C622oEN-C ...
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... The input jitter tolerance of the ZL30414 is shown in Figure 4. On this graph, the single line at the top represents measured input jitter tolerance and the three overlapping lines below represent minimum input jitter tolerance for OC-192, OC-48, and OC-12 network interfaces ...
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... Jitter Transfer Characteristic represents a ratio of the jitter at the output of a PLL to the jitter applied to the input of a PLL. This ratio is expressed in dB and it characterizes the PLLs ability to attenuate (filter) jitter. The jitter transfer characteristic for the ZL30414 configured with recommended loop filter components (R shown in Figure 5. The plotted curves represent jitter transfer characteristics over the recommended voltage (3 ...
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... The ZL30414 functionality and performance complements the entire family of the Zarlink’s advanced network synchronization PLLs. Its superior jitter filtering characteristics exceed requirements of SONET/SDH optical interfaces operating up to OC-192/STM-64 rate (10 Gbit/s). The ZL30414 in combination with the MT90401 or the ZL30407 (SONET/SDH Network Element PLLs) provides the core building blocks for high quality equipment clocks suitable for network synchronization (see Figure 6) ...
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... The ZL30414 in combination with the MT9046 provides an optimum solution for SONET/SDH line cards (see Figure 7). C19i R = 680 : 820 PRI SEC Synchronization Reference RSEL Clocks LOCK HOLDOVER C20i 20 MHz TCXO Note: Only main functional connections are shown ...
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... The C155o output provides a differential CML/LVDS compatible clock at 155.52 MHz. The output drivers require load at the terminating end if the receiver is CML type. ZL30414 VCC CML Driver 155.52 MHz GND ZL30414 +3.3 V 0.1 uF Z=50 : C622oP-A Z=50 : C622oN-A Typical resistor values 130 :, R2 =82 : Figure 8 - LVPECL to LVPECL Interface +3 ...
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... CML to LVPECL Interface The CML output can drive LVPECL input as is shown in Figure 11. The terminating resistors should be placed as close as possible to the LVPECL receiver. ZL30414 VCC CML Driver 155.52 MHz GND ZL30414 +3 Z= Typical resistor values k Figure 10 - LVDS Termination +3 ...
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... Tristating LVPECL Outputs The ZL30414 has four differential 622.08 MHz LVPECL outputs, which can be used to drive four different OC-3/OC- 12/OC-48/OC-192 devices such as framers, mappers and SERDES. In the case where fewer than four clocks are required, a user can disable unused LVPECL outputs on the ZL30414 by pulling the corresponding enable pins low. ...
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... All the ground pins (GND) and the Exposed die Pad (metal area at the back of the package) are connected to the same ground plane. 2. Select Ferrite Bead with I DC Figure 13 - Power Supply and BIAS Circuit Filtering ZL30414 0.1 uF 0.1 uF GND VCC1 2 VCC 0 GND VCC2 8 ZL30414 + 0 GND GND 10 BIAS 0 0.1 uF > 400 mA and range from 0 ...
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... LVPECL driver (driver enabled and terminated, see Figure 8) 3 Incremental Supply Current to CML driver (driver enabled and terminated, see Figure 9) 4 CMOS: High-level input voltage 5 CMOS: Low-level input voltage 6 CMOS: Input leakage current ZL30414 ‡ Sym. Min TBD DDR CCR V -0.5 PIN I -0.5 PIN ...
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... LVPECL outputs. More than 25% of this current LVPECL flows outside the chip and it does not contribute to the internal power dissipation. - Note 2: LVPECL outputs terminated with Z - Note 3: CML outputs terminated with Z ZL30414 Sym. Min. Typ. I 300 B-PU ...
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... Threshold Voltage 2 Rise and Fall Threshold Voltage High 3 Rise and Fall Threshold Voltage Low † Voltages are with respect to ground unless otherwise stated. All Signals Figure 14 - Output Timing Parameter Measurement Voltage Levels ZL30414 Sym CMOS LVPECL V 0.5V 0.5V T-CMOS DD V T-LVPECL V ...
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... Supply voltage and operating temperature are as per Recommended Operating Conditions ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. C19i (19.44 MHz) C19o (19.44 MHz) C155o (155.52 MHz) C622oA (622.08 MHz) Figure 15 - C19i Input to C19o, C155o and C622o Output Timing ZL30414 ‡ Sym. Min. Typ. t 6.2 7.2 C19D tc 3 ...
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... Supply voltage and operating temperature are as per Recommended Operating Conditions ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. C622oA C622oB C622oC C622oD Note: All output clocks have nominal 50% duty cycle. Figure 16 - C622oB, C622oC, C622oD Outputs Timing ZL30414 ‡ Sym. Min. Typ. t -50 0 ...
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... Typ. limit in time UI domain 0.1 UI 10.0 PP 0.01 UI 1.0 0.52 RMS 0.1 UI 40.2 PP 0.01 UI 4.02 0.58 RMS 0.1 UI 161 PP 0.01 UI 16.1 0.34 RMS 20 Zarlink Semiconductor Inc. Data Sheet Units Notes ppm At nominal input reference frequency C19i = 19.44 MHz 3.3V ±10%; CC ZL30414 Jitter Generation Performance † ‡ Max. Units - 7.31 ps P-P 0.94 ps RMS - 7.32 ps P-P 0.83 ps RMS - 4.37 ps P-P 0.60 ps RMS ...
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... Typ. limit in time UI domain 0.1 UIpp 10.0 0.49 0.5 UIpp 50.2 0.82 0.1 UIpp 40.2 0.50 0.5 UIpp 201 0.68 0.1 UIpp 161 0.26 0.5 UIpp 804 1.51 0.1 UIpp 10.0 0.49 0.3 UIpp 30.1 0.82 0.1 UIpp 40.2 0.58 0.1 UIpp 161 0.34 21 Zarlink Semiconductor Inc. Data Sheet (V = 3.3V CC ZL30414 Jitter Generation Performance † ‡ Max. Units - 6.95 ps P-P 0.89 ps RMS - 11.5 ps P-P 1.04 ps RMS - 6.40 ps P-P 0.68 ps RMS - 8.67 ps P-P 1.06 ps RMS - 3.33 ps P-P 0.42 ps ...
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... Loop Filter components: R =8.2 k:C =470 ZL30414 Equivalent Limit in Typ. limit in time UI domain 0.1 UIpp 40.2 0.50 0.5UIpp 201 0.68 0.1 UIpp 161 0.26 0.5 UIpp 804 1.51 22 Zarlink Semiconductor Inc. Data Sheet (V = 3.3V CC ZL30414 Jitter Generation Performance † ‡ Max. Units - 6.40 ps P-P 0.68 ps RMS - 8.67 ps P-P 1.06 ps RMS - 3.33 ps P-P 0.42 ps RMS - 19.1 ps P-P 2 ...
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... Zarlink Semiconductor 2005 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...