zl30120 Zarlink Semiconductor, zl30120 Datasheet - Page 22

• Manufacturer Part Number: zl30120
• Description: Sonet/sdh/ethernet Multi-rate Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

(Hex)
Addr
4A
4B
4C
4D
4E
42
43
44
45
46
47
48
49
4F
50
51
52
53
p0_fp0_offset_2
p0_fp1_freq
p0_fp1_type
p0_fp1_offset_0
p0_fp1_offset_1
p0_fp1_offset_2
p1_enable
p1_run
p1_freq_0
p1_freq_1
p1_clk0_offset90
p1_clk1_div
p1_clk1_offset90
p1_offset_fine
apll_enable
apll_run
apll_clk_div
apll_clk0_offset90
Register
Name
Reset
Value
(Hex)
C1
00
05
00
00
00
83
03
00
00
3F
00
00
8F
0F
42
00
11
APLL Configuration Registers
Zarlink Semiconductor Inc.
P1 Configuration Registers
ZL30120
Bits [21:16] of the programmable frame pulse
Control register to select p0_fp1 frame pulse
Control register to select fp1 type
Bits [7:0] of the programmable frame pulse
Bits [15:8] of the programmable frame pulse
Bits [21:16] of the programmable frame pulse
Control register for the [7:0] bits of the N of
Control register for the p1_clk0 phase position
Control register for the p1_clk1 frequency
Control register for the p1_clk1 phase position
Control register to generate apll_clk0,
Control register for the apll_clk0 phase position
phase offset in multiples of 8 kHz cycles
frequency
phase offset in multiples of 1/262.144 MHz
phase offset in multiples of 1/262.144 MHz
phase offset in multiples of 8 kHz cycles
Control register to enable p1_clk0, p1_clk1, the
P1 synthesizer and select the source
Control register to generate enable/disable
p1_clk0 and p1_clk1
N*8k clk0
Control register for the [13:8] bits of the N of
N*8k clk0
coarse tuning
selection
coarse tuning
Control register for the output/output phase
alignrment fine tuning
Control register to enable apll_clk0, apll_clk1,
apll_fp0, apll_fp1 and the APLL
apll_clk1, apll_fp0 and apll_fp1
Control register for the apll_clk0 and apll_clk1
frequency selection
coarse tuning
22
Description
Data Sheet
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W