zl30120 Zarlink Semiconductor, zl30120 Datasheet - Page 11

• Manufacturer Part Number: zl30120
• Description: Sonet/sdh/ethernet Multi-rate Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

1.0
The ZL30120 Multi-Rate Line Card Synchronizer is a highly integrated device that provides timing and
synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one
of eight input references and provides a wide variety of synchronized output clocks and frame pulses.
1.1
The ZL30120 provides two independently controlled Digital Phase-Locked Loops (DPLL1, DPLL2) for clock and/or
frame pulse synchronization. DPLL1 is the main DPLL and is always enabled. To save on power, DPLL2 is disabled
by default. For applications where DPLL2 is required, it must be enabled using the dpll_en bit of the dpll2_ctrl_0
register (0x2A). Table 1 shows a feature summary for both DPLLs.
Modes of Operation
Loop Bandwidth
Phase Slope Limiting
Pull-in Range
Holdover Parameters
Holdover Frequency
Accuracy
Reference Inputs
Sync Inputs
Input Reference
Selection/Switching
Hitless Ref Switching
Output Clocks
Output Frame Pulses
External Pins Status
Indicators
1. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies equal to or
greater than 64 kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to or greater than 8 kHz and less than 64 kHz, the
loop bandwidth = 56 Hz. For reference frequencies equal to 2 kHz, the loop bandwidth is equal to 14 Hz.
DPLL Features
Functional Description
Feature
Free-run, Normal (locked), Holdover
User selectable: 14 Hz, 28 Hz, or
wideband
User selectable: 885 ns/s, 7.5 2s/s,
61 2s/s, or unlimited
Fixed: 130 ppm
Selectable Update Times: 26 ms, 1 s,
10 s, 60 s, and Selectable Holdover
Post Filter BW: 18 mHz, 2.5 Hz, 10 Hz.
Better than 1 ppb (Stratum 3E) initial
frequency offset. Frequency drift
depends on the 20 MHz external
oscillator.
Ref0 to Ref7
Sync0, Sync1, Sync2
Automatic (based on programmable
priority and revertiveness), or manual
Can be enabled or disabled
apll_clk0, apll_clk1, p0_clk0, p0_clk1,
p1_clk0, p1_clk1, fb_clk.
apll_fp0, apll_fp1, p0_fp0, p0_fp1
synchronized to active sync reference.
Lock, Holdover
Table 1 - DPLL1 and DPLL2 Features
1
(890 Hz / 56 Hz / 14 Hz)
DPLL1
Zarlink Semiconductor Inc.
ZL30120
11
Free-run, Normal (locked), Holdover
Fixed: 14 Hz
User selectable: 61 2s/s, or unlimited
Fixed: 130 ppm
Fixed Update Time: 26 ms
No Holdover Post Filtering
Better than 50 ppb (Stratum 3) initial
frequency offset. Frequency drift
depends on the 20 MHz external
oscillator.
Ref0 to Ref7
Sync inputs are not supported.
Automatic (based on programmable
priority and revertiveness), or manual
Can be enabled or disabled
p0_clk0, p0_clk1, p1_clk0, p1_clk1.
p0_fp0, p0_fp1 not synchronized to sync
reference.
None
DPLL2
Data Sheet