zl30122 Zarlink Semiconductor, zl30122 Datasheet - Page 19

• Manufacturer Part Number: zl30122
• Description: Sonet/sdh Low Jitter Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

(Hex)
Addr
5B -
5A
6A
6B
54
55
56
57
58
59
5F
60
61
62
63
64
65
66
67
68
69
Reserved
sdh_offset_fine
sdh_fp_freq
sdh_fp_type
sdh_fp_fine_offset_0
sdh_fp_fine_offset_1
sdh_fp_coarse_offset
Reserved
diff_clk_ctrl
diff_clk_sel
Reserved
fb_offset_fine
reserved
ref_freq_mode_0
Reserved
custA_mult_0
custA_mult_1
custA_scm_low
custA_scm_high
custA_cfm_low_0
Register
Name
Table 5 - Register Map (continued)
Custom Input Frequencies
Reset
Value
(Hex)
Differential Output Configuration
External Feedback Configuration
A3
00
05
23
00
00
00
53
F5
00
00
00
00
00
00
Zarlink Semiconductor Inc.
ZL30122
Leave as default
Control register for the output/output phase
Control register to select the sdh_fp frame
Control register to select sdh_fp type
Bits [7:0] of the programmable frame pulse
Programmable frame pulse phase offset in
Control register to enable diff_clk
Control register to select the diff_clk frequency
Leave as default
Control register to set whether to use auto
Leave as default
Control register for the [7:0] bits of the custom
Control register for the [13:8] bits of the custom
Control register for the custom configuration A:
Control register for the custom configuration
alignrment fine tuning for sdh path
pulse frequency
phase offset in multiples of 1/311.04 MHz
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
multiples of 8 kHz cycles
Leave as default
Control register for the output/output phase
alignment fine tuning
detect, CustomA or CustomB for ref0 to ref2
configuration A. This is the N integer for the
N*8kHz reference monitoring.
configuration A. This is the N integer for the
N*8kHz reference monitoring.
single cycle SCM low limiter
Control register for the custom configuration
A: single cycle SCM high limiter
A: The [7:0] bits of the single cycle CFM low
limit
19
Description
Data Sheet
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W