zl30122 Zarlink Semiconductor, zl30122 Datasheet - Page 17

• Manufacturer Part Number: zl30122
• Description: Sonet/sdh Low Jitter Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

(Hex)
Addr
1A
1B
1C
1D
1E
14
15
16
17
18
19
1F
20
21
22
23
24
25
26
27
detected_sync_0
detected_sync_1
oor_ctrl_0
oor_ctrl_1
Reserved
Reserved
gst_mask
Reserved
gst_qualif_time
dpll_ctrl_0
dpll_ctrl_1
dpll_modesel
dpll_refsel
dpll_ref_fail_mask
dpll_wait_to_restore
dpll_ref_rev_ctrl
dpll_ref_pri_ctrl_0
dpll_ref_pri_ctrl_1
Reserved
Reserved
Register
Name
Table 5 - Register Map (continued)
Description
Description
Description
Register
Register
Register
Reset
Value
(Hex)
See
See
See
EE
0E
FF
1A
3C
33
33
00
00
00
10
32
Zarlink Semiconductor Inc.
ZL30122
DPLL Control
Sync2 auto-detected frequency value and sync
Control register for the ref0 and ref1 out of
Leave as default
Leave as default
Leave as default
Control register to mask each failure indicator
Control register for the ref0 to ref2 enable
Control register for the ref0 and ref1 priority
Sync0 and sync1 auto-detected frequency
value and sync failure status register
valid status register
range limit
Control register for the ref2 out of range limit
Control register to mask the inputs to the guard
soak timer for ref0 - ref2
Control register for the guard_soak_timer
qualification time and disqualification time for
the references
Control register for the DPLL filter control;
phase slope limit, bandwidth and hitless
switching
Holdover update time, filter_out_en,
freq_offset_en, revert enable
Control register for the DPLL mode of
operation
DPLL reference selection or reference selection
status
(SCM, CFM, PFM and GST) used for automatic
reference switching and automatic holdover
Control register to indicate the time to restore a
previous failed reference
revertive signals
values
Control register for the ref2 priority values
Leave as default
Leave as default
17
Description
Data Sheet
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R