m21315 Mindspeed Technologies, m21315 Datasheet - Page 7

• Manufacturer Part Number: m21315
• Description: M21315 Hd/sd-sdi Auto-rate Reclocker W/4 1 Selector
• Manufacturer: Mindspeed Technologies

1.1
1.1.1
The M21315 reclocker is a dual-loop based design. The primary phase-locked loop (PLL) functions to 1) lock the
VCO to the incoming data rate and 2) to retime the incoming data to remove jitter. In general, the VCO tuning range
for a multi-rate design is much larger than the frequency pull-in range of the reclocker phase detector. As a result, a
secondary frequency-locked loop (FLL) is added to tune the VCO to the approximate data frequency so the clock
and data recovery unit (CDR) can lock onto valid data. The FLL uses an external crystal as an absolute frequency
reference. As a result, the external reference is only used to assist the CDR frequency locking and the jitter
performance of the reference has no effect on the recovered data output jitter.
1.1.2
When the reclocker is out of lock (LOL = Low), the FLL is enabled. The FLL compares the input data to the external
reference and drives the VCO towards a target frequency that is very close to the incoming data rate frequency.
The FLL is shut off when the VCO frequency and the frequency of the input data are within +/- 2000 ppm of each
other. When FLL is shut off, LOL = High, to indicate a lock condition. If data is present, then the phase lock loop of
the reclocker will lock to the incoming data. When in lock, the FLL control circuit continues to monitor the frequency
difference between the VCO and the reference. If the difference exceeds +/- 3000 ppm, a loss of lock condition is
indicated and frequency acquisition is initiated. If there is no input data present, an internal loss of signal detector
will keep LOL=Low until an input signal has been detected. The output signal from the reclocker is undefined when
there is no valid signal at the input of the reclocker. When a valid input signal is detected, frequency acquisition is
initiated and the reclocker will lock to the appropriate data rate.
1.2
1.2.1
Throughout this data sheet, physical pins will be denoted in bold print. An array of pins can be called by each
individual pin name (e.g. MF0, MF1, MF2, MF3, and MF6) or as an array (e.g. MF[0..3,6] or MF[0:3,6]).
21315-DSH-001-B
General Description
Reclocker General Overview
Frequency Acquisition
Pin Descriptions
General Nomenclature
1.0 Functional Description
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