mt8986al1 Zarlink Semiconductor, mt8986al1 Datasheet - Page 12

• Manufacturer Part Number: mt8986al1
• Description: Multiple Rate Digital Switch
• Manufacturer: Zarlink Semiconductor

MT8986
Data Sheet
Microprocessor Port
The non-multiplexed bus interface provided by the MT8986 device is identical to that provided in MT8980 Digital
Switch device. In addition to the non-multiplexed bus, the MT8986 device provides an enhanced microprocessor
interface with multiplexed bus structure compatible to both Motorola and Intel buses. The multiplexed bus structure
is available only in the 44 pin packages and it is selected by the CPU Interface Mode (IM) input pin.
If IM input pin is not connected (left open) or grounded, the MT8986 parallel port assumes its default Motorola non-
multiplexed bus mode identical to that of MT8980. If IM input is connected HIGH, the internal parallel microport
provides compatibility to MOTEL interface allowing direct connection to Intel, National and Motorola CPUs.
The MOTEL circuit (MOtorola and InTEL compatible bus) automatically identifies the type of CPU Bus connected to
the MT8986 device. This circuit uses the level of the DS/RD input pin at the rising edge of the AS/ALE to identify
the appropriate bus timing connected to the MT8986. If DS/RD is LOW at the rising edge of AS/ALE then Motorola
bus timing is selected. If DS/RD is HIGH at the rising edge of AS/ALE, then Intel bus timing is selected.
When MT8986 parallel port is operating in Motorola, National or Intel multiplexed bus interfaces, the signals
available for controlling the device are: AD0-AD7 (Data and Address), ALE/AS (Address Latch Enable/Address
Strobe), DS/RD (Data Strobe/Read), R/W\WR (Read/Write\Write), CS (Chip Select) and DTA (Data
Acknowledgement). In Motorola non-multiplexed bus, the interface control signals are: data bus (AD0-AD7), six
address input lines (A0-A5) and four control lines (CS , DS, R/W and DTA). See Figures 26 to 28 for each CPU
interface timing.
The MT8986 parallel microport provides the access to the IMS, Control registers, the Connection Memory High, the
Connection Memory Low and the Data Memory. All locations can be read or written except for the data memory
which can be read only.
Software Control
The address bus on the microprocessor interface selects the internal registers and memories of the MT8986. If the
A5 address input is LOW, then the MT8986 Internal Control, Interface Mode, Stream Pair Selection and Frame
Input Offset registers are addressed by the A4 to A0 bits according to Table 5. If A5 input is HIGH, then the
remaining address input lines are used to select memory subsections of up to 128 locations corresponding to the
maximum number of channels per input or output stream. The address input lines and the Stream Address bits
(STA) of the Control register give the user the capability of accessing all sections of the MT8986 Data and Connect
memories.
The Control and Interface Mode Selection registers together control all the major functions of the device. The
Interface Mode Select register should be set up during system power-up to establish the desired switching
configuration as explained in the Serial Interface and Switching Configurations sections.
The Control register is dynamically used by the CPU to control switching operations in the MT8986. The Control
register selects the device's internal memories and its subsections to specify the input and output channels
selected for switching procedures.
The data in the Control register consists of Split memory and Message mode bits, Memory select and Stream
Address bits. The memory select bits allow the Connect Memory HIGH or LOW or the Data Memory to be chosen,
and the Stream Address bits define an internal memory subsections corresponding to input or output ST-BUS
streams.
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