mt8986al1 Zarlink Semiconductor, mt8986al1 Datasheet - Page 11

• Manufacturer Part Number: mt8986al1
• Description: Multiple Rate Digital Switch
• Manufacturer: Zarlink Semiconductor

Different I/O Data Rates
Except for 2 Mb/s to 4 Mb/s and 2 Mb/s to 8 Mb/s rate conversion operations, the throughput delay in the MT8986
may vary according to the output stream used for switching.
Table 3b explains the worst case conditions for the throughput delay when different I/O data rate switching
configurations are used.
Notes: dmin and dmax are measured in time-slots and at the point in time when the output channel is completely shifted out.
Constant Throughput Delay mode (V/C bit = 1)
In this mode frame sequence integrity is maintained in both Identical and Different I/O Data Rate operations by
making use of a multiple Data-Memory buffer technique. The input channels written in any of the buffers during
frame N will be read out during frame N+2. In applications at 2.048 Mb/s for instance, the minimum throughput
delay achievable in constant delay mode will be 32 time-slots; for example, when input time-slot 32 (channel 31) is
switched to output time-slot 1 (channel 0). Likewise, the maximum delay is achieved when the first time slot in a
frame (channel 0) is switched to the last time-slot in the frame (channel 31), resulting in 94 time-slots of delay.
To summarize, any input time-slot from input frame N will always be switched to the destination time-slot on output
frame N+2. Table 4 describes the MT8986 constant throughput delay values for different data rates.
2 Mb/s to 4 Mb/s
2 Mb/s to 8 Mb/s
4 Mb/s to 2 Mb/s
8 Mb/s to 2 Mb/s
I/O Data Rate
Configuration
t.s. = time-slot
fr. = 125 µs frame
2 Mb/s t.s. = 3.9 µs
4 Mb/s t.s. = 1.95 µs
8 Mb/s t.s. = 0.975 µs
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Data Rate
Table 3b - Min/Max Throughput Delay Values for Different I/O Rate Applications
dmin=5x 4Mb/s t.s.
dmax=1 fr.+(4x 4Mb/s t.s.)
dmin=9x 8Mb/s t.s.
dmax=1 fr.+(8x 8Mb/s t.s.)
dmin=3x 2Mb/s t.s.
dmax=1 fr.+(2x 2Mb/s t.s.)
dmin=3x 2Mb/s t.s.
dmax=1 fr.+(2x 2Mb/s
0, 1
Table 4 - Constant Throughput Delay values
t.s.)
d=[128 + (128 - IN) + (OUT - 1)]; (expressed in # time-slots)
2.048 Mb/s time-slot: 3.9µs
IN: input time-slot (from 1 to 32)
OUT: output time-slot (from 1 to 32)
IN: input time-slot (from 1 to 64)
OUT: output time-slot (from 1 to 64)
8.192 Mb/s time-slot: 0.975 µs
IN: input time-slot (from 1 to 128)
OUT: output time-slot (from 1 to 128)
dmin=(2x 2Mb/s t.s.)+
dmax=1 fr.+(1x 2Mb/s
4.096 Mb/s time-slot: 1.95 µs
d=[32 + (32 - IN) + (OUT - 1)]; (expressed in # time-slots)
d=[64 + (64 - IN) + (OUT - 1)]; (expressed in # time-slots)
Zarlink Semiconductor Inc.
(3x 8Mb/s t.s.)
t.s.)+(3x 8Mb/s t.s.)
MT8986
2, 3
11
Output Stream Used
Throughput Delay (d)
dmin=(2x 2Mb/s t.s.)+(1x 4Mb/s t.s.)
dmax=1 fr.+(1x 2Mb/s t.s.)+(1x 4Mb/s t.s.)
dmin=(2x 2Mb/s t.s.)+
dmax=1 fr.+(1x 2Mb/s
(2x 8Mb/s t.s.)
t.s.)+(2x 8Mb/s t.s.)
4, 5
dmin=(2x 2Mb/s t.s.)+
dmax=1 fr.+(1x 2Mb/s
(1x 8Mb/s t.s.)
t.s.)+(1x 8Mb/s t.s.)
Data Sheet
6, 7