mt8980dpr1 Zarlink Semiconductor, mt8980dpr1 Datasheet - Page 13

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mt8980dpr1

Manufacturer Part Number
mt8980dpr1
Description
256 X 256 Channels 8 Tdm Streams At 2.048 Mbps Non-blocking Digital Switch Dx
Manufacturer
Zarlink Semiconductor
Datasheet

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Part Number:
MT8980DPR1
Manufacturer:
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Quantity:
117
AC Electrical Characteristics
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
* Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state.
NB: Frame Pulse is repeated every 512 cycles of C4i.
1
2
3
4
5
6
7
C4i
F0i
BIT
CELLS
N
U
P
T
S
I
Output
Pin
Clock Period*
Clock Width High
Clock Width Low
Clock Transition Time
Frame Pulse SetupTime
Frame Pulse Hold Time
Frame Pulse Width
Characteristics
°
C and are for design aid only: not guaranteed and not subject to production testing.
C
L
Test Point
V
SS
- Clock Timing (Figures 12 and 13)
Channel 31
S1
Bit o
Figure 11 - Output Test Load
Figure 12 - Frame Alignment
Sym.
t
t
t
t
t
t
Zarlink Semiconductor Inc.
CLK
t
FPW
CTT
FPS
FPH
CH
CL
R
L
MT8980D
0.020
Min.
220
110
95
20
13
S2
V
Typ.
SS
V
244
122
122
244
20
DD
Max.
when testing output levels
or high impedance states.
V
levels or high impedance
states.
300
150
150
200
50
SS
S1 is open circuit except
S2 is switched to V
when testing output
Units
ns
ns
ns
ns
ns
µs
ns
Channel 0
Bit 7
DD
or
Test Conditions
Data Sheet

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