ml87v3116 Oki Semiconductor, ml87v3116 Datasheet
ml87v3116
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ml87v3116 Summary of contents
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... Imaging functions, such as image input, temporary storage, processing and display output, are integrated into a single chip. The ML87V3116 has functions includuing camera or video input image capture, display control in LCD or TV format, compression and decompression of still pictures and moving pictures (Motion-JPEG) using a JPEG engine, and image copying with the size reduction and the rotation ...
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... Host interface 8/16-bit CPU bus External Data buffer SDRAM (1 Mbytes) D16 D64 16 Data buffer controller Rectangle JPEG copy Codec controller Clock/power Memory stick manager controller SD/MMC or Memory stick PEDL87V3116-02 ML87V3116 YCbCr /RGB Display 18/24 Display Output controller Peripheral SPI control SD/MMC controller 2/47 ...
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... OKI Semiconductor PIN CONFIGURATION (TOP VIEW) 132 133 176 1 Index mark (top side) 176-Pin Plastic LQFP PEDL87V3116-02 ML87V3116 3/47 ...
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... Display data R, bit 0 or frame drive pulse 3 I/O O 4mA drive Data clock O 4mA drive Line drive pulse 1 (HSYNC) Input LVTTL I/O Horizontal start signal 1 (GPIO3) O 4mA drive Frame drive pulse 1 (VSYNC) O 4mA drive Current-alternating signal/field ID signal O 4mA drive Display enable PEDL87V3116-02 ML87V3116 Description Description 4/47 ...
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... LVTTL Host access chip select I LVTTL Host read enable I LVTTL Host write enable I LVTTL Host bus strobe I LVTTL Host data strobe 4mA drive O Bus busy/wait 3 states I LVTTL Bus clock O 4mA drive Interrupt I LVTTL Host bus mode select PEDL87V3116-02 ML87V3116 Description Description 5/47 ...
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... I LVTTL SD card interface write protect O 4mA drive SD card interface power control I/O Type I LVTTL Reference clock I LVTTL System reset I LVTTL Test mode (all fixed to "L") O 4mA drive Test output (open) I LVTTL Test mode (fixed to "L") PEDL87V3116-02 ML87V3116 Description Description 6/47 ...
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... VSS1 110, 132, 133, 169 8, 22, 64, 89, VDD2 114, 152, 162 1, 15, 58, 96, VSS2 120, 145, 157 44 VDDP 43 VSSP Description I/O power supply (3.3V) I/O ground Core power supply (2.0V) Core ground PLL power supply PLL ground PEDL87V3116-02 ML87V3116 7/47 ...
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... OKI Semiconductor FUNCTIONAL DESCRIPTION 1. General Description The ML87V3116 is comprised of the following blocks. 1.1 Video Input Interface The video input interface has two video input ports, and stores image data input from either port into the Data Buffer. 1.2 Display Interface The display interface outputs image data written into the Data Buffer to the external display unit. ...
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... Field ID polarity, 1 bit (write/read) • HSCYC : Horizontal synchronous signal cycle, 12 bits (read only) • VSCYC : Vertical synchronous signal cycle, 12 bits (read only) • HVDET : VHS signal, VVS signal detection, 1 bit (read only) • IPDET : Interlace/progressive detection, 1 bit (read only) PEDL87V3116-02 ML87V3116 9/47 ...
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... Use the following frames rate as a guide in the continuous capture mode. • 720 x 480 pixels: 30 frames/sec max. • million pixels: 15 frames/sec max. • million pixels: 10 frames/sec max. • million pixels: 3 frames/sec max. [HSCYC] [VISTAH] [VIACTH] Active Video PEDL87V3116-02 ML87V3116 10/47 ...
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... VIFITV : Frame thinning rate, 4 bits (write/read) “0000”: 1/1, “0001”: 1/2, …, “1110”: 1/15, “1111”: 1/16 • VCAPAX : Data buffer X address, 8-pixel unit 12 bits (write/read) • VCAPAY : Data buffer Y address, 1- (or 8-) line unit 12 bits (write/read) PEDL87V3116-02 ML87V3116 11/47 ...
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... VSYNC (vertical synchronous signal) (Not used) (Not used) Field ID signal Display enable PEDL87V3116-02 ML87V3116 Remarks Pulse width Pulse width Possible to AND with LDP4 Possible to OR with LDP2 12/47 ...
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... These settings can be changed in the TFT-LCD mode. However, the values set are held even after switching to the TV mode; thus, display can be performed in the original state when returning to the TFT-LCD mode again. The “LDP2-4,” “HST1, 2” and “FDP2-3” signals can be used as GPIOs if they are not used as synchronous signals. PEDL87V3116-02 ML87V3116 13/47 ...
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... ACTHST : Horizontal start position of effective image data, 11 bits (write/read) • ACTHED : Horizontal end position of effective image data, 11 bits (write/read) • ACTVST : Vertical start position of effective image data, 10 bits (write/read) • ACTVED : Vertical end position of effective image data, 10 bits (write/read) PEDL87V3116-02 ML87V3116 14/47 ...
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... GPIO that corresponds to the bits of the input mode is read. Reading the bits of the output mode and writing to the bits of the input mode are disabled. Figure 2.2 Output Synchronization Timing [HLCYC] Internal HS HSTn [HSTnPOS] LDPn [LDPnST] [LDPnED] [ACTHED] [ACTHST] PEDL87V3116-02 ML87V3116 Active Image 15/47 ...
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... Cb1 Cb2 Cb3 Cb4 Cr1 Cr2 Cr3 Cr4 Cr0 Cb2 Cr2 Cb4 Figure 2.3 Display Data Formats PEDL87V3116-02 ML87V3116 Cb5 Cb6 Cb7 Cr5 Cr6 Cr7 Cb6 Cr4 Cr6 16/47 ...
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... All “L”, “1”: All “H” • DOPSNG : Positive/negative mode of output data, 4 bits (write/read) “0”: Normal mode (positive), “1”: All bits reversed (negative) • DISP : DISP signal output level, 1 bit (write/read) “0”: “L” level, “1”: “H” level PEDL87V3116-02 ML87V3116 17/47 ...
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... OKI Semiconductor Horizontal Partition Mode Area 0 Area 1 Area 2 Area 3 [ACTHED] - [ACTHST] Vertical Partition Mode Area 0 Area 1 Area 2 Area 3 [ACTHED] - [ACTHST] Figure 2.4 Display Area Partitioning PEDL87V3116-02 [DIVAP1] [DIVAP2] [DIVAP3] Display screen [DIVAP1] [DIVAP2] [DIVAP3] Display screen ML87V3116 18/47 ...
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... OKI Semiconductor Data buffer [DA1SAX] [DA3SAX] [DA1SAY] [DA3SAY] [DA0SAX] [DA0SAY] [DA2SAX] [DA2SAY] Figure 2.5 Display Address Specification (Example in Vertical Partition Mode) PEDL87V3116-02 ML87V3116 Display outputs Area 0 Area 1 Area 2 Area 3 19/47 ...
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... When playing back (decompressing) moving pictures, the operation is synchronized with the frame timing of video output. During an moving picture recording operation, the same image size, quantization table and Huffman table are used for all frames. They cannot be changed during recording. PEDL87V3116-02 ML87V3116 20/47 ...
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... One or two locations can be specified as the source image read addresses when compressing and playback image write addresses when decompressing. If two locations are specified at the same time, they can alternately be switched for each frame. When playing back moving pictures, a double-buffer operation can be performed, achieving smooth moving picture display. PEDL87V3116-02 ML87V3116 21/47 ...
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... Cb, Cr) specified from the host CPU. Read data in a rectangle area in the Data Buffer by the host CPU. 4 Host Access Also, write data sent from the host CPU into a rectangle area in the Data Buffer Table 2.4.1 Copy Function List Functional description . PEDL87V3116-02 ML87V3116 Note Buffer, and copy 22/47 ...
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... Be sure to specify a rectangle area within the range of the buffer memory size in use. Buffer memory area Copy source (Xfrom_adrs, Yfrom_adrs) Vertical Ysize Y Figure 2.4.2 Image of Rectangle Area Specification Horizontal X Copy destination (Xto_adrs, Yto_adrs) Xsize Copy Copy source For copy (rotation) PEDL87V3116-02 ML87V3116 Copy destination Copy destination 23/47 ...
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... Copy destination (specified coordinates) (Xto_adrs, Yto_adrs) 270° rotation Figure 2.4.3 Example of Copy Destination Coordinate Specification and Processing Sequence for Copy by Rotating 16 pixels 4 lines 16 pixels 4 lines 16×16 pixels Ysize Xsize 180° rotation PEDL87V3116-02 ML87V3116 Buffer memory area 0° rotation 90° rotation 24/47 ...
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... However, JPEG accesses of c) and d) are always carried out simultaneously in pair. Also, during the operations of the copy functions e) and f), the host access g) cannot be carried out simultaneously. For access to an extension data buffer, always only one access source can be used. PEDL87V3116-02 ML87V3116 25/47 ...
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... Vertical (24703 lines max.) Vertical (4940 lines max.) Vertical (98815 lines max.) Vertical (197631 lines max.) Vertical Horizontal (1023 pixels max.) Horizontal (2047 pixels max.) Internal sdram External sdram Figure 2.5.1 Image of Buffer Memory Size PEDL87V3116-02 ML87V3116 Horizontal (4095 pixels max.) 26/47 ...
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... Y(max) Inv alid Y(min) X(max) = 1024 Y 25 bits row -1 row Figure 2.5.3 Address Conversion PEDL87V3116-02 ML87V3116 X(min) = 128 Example of Xsize = 512 X Make the least significant 2 bits of Y and X as the least significant 4 bits of an one-dimensional address. Internal data buffer col (8192x16x64b) Example ...
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... BSN, RWN, DSN, Renesas M32R, NEC V830 Busy Intel SA-110 (Reserved) — Renesas SH-1, SH-2 ASN, WEN, REN, NEC V850, 78K/IV Busy Renesas M16C Oki MSM66K, 80C51 2 Fujitsu F MC-16L AS, WEN, REN, Toshiba TLCS-900 Busy Renesas M16C Oki MSM66K, 80C51 (Reserved) — PEDL87V3116-02 ML87V3116 *1) *2) 28/47 ...
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... CSN CSN CSN REN REN RWN WEN WEN — BS BSN BSN — — — BSYN ACK ACK BCLK BCLK BCLK PEDL87V3116-02 ML87V3116 A18-16 A18-16 A18-16 A15-00 AD15-00 AD15-00 D07-00 — — REGS REGS REGS CSN CSN CSN RWN REN REN — ...
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... OKI Semiconductor [Bus Interface Timing] (1) A0-Type Write BCLK CSN REGS A18-00 REG WEN (z) D7-0 (write) BSYN (2) A0-Type Read BCLK CSN REGS A18-00 REG REN (z) D7-0 (read) BSYN PEDL87V3116-02 ML87V3116 MEM MEM 30/47 ...
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... OKI Semiconductor (3) A1-Type Write BCLK CSN BS REGS A18-00 REG WEN (z) D7-0 (write) BSYN (4) A1-Type Read BCLK CSN BS REGS A18-00 REG REN (z) D7-0 (read) BSYN PEDL87V3116-02 ML87V3116 MEM MEM 31/47 ...
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... OKI Semiconductor (5) A2-Type Write BCLK CSN BSN REGS A18-00 REG WEN (z) D7-0 (write) ACK (6) A2-Type Read BCLK CSN BSN REGS A18-00 REG REN (z) D7-0 (read) ACK PEDL87V3116-02 ML87V3116 MEM MEM 32/47 ...
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... OKI Semiconductor (7) A4-Type Write BCLK CSN BSN REGS A18-00 REG RWN (z) D7-0 (write) ACK (8) A4-Type Read BCLK CSN BSN REGS A18-00 REG RWN (z) D7-0 (read) ACK PEDL87V3116-02 ML87V3116 MEM MEM 33/47 ...
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... OKI Semiconductor (9) A5-Type Write BCLK CSN BSN REGS A18-00 REG RWN (z) D7-0 (write) BSYN (10) A5-Type Read BCLK CSN BSN REGS A18-00 REG RWN (z) D7-0 (read) BSYN PEDL87V3116-02 ML87V3116 MEM MEM 34/47 ...
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... OKI Semiconductor (11) B0-Type Write BCLK CSN ASN REGS A18-16 WEHN WELN (z) AD15-0 A BSYN (12) B0-Type Read BCLK CSN ASN REGS A18-16 REN (z) AD15-0 A BSYN D (write (read) PEDL87V3116-02 ML87V3116 D (write) D (read) 35/47 ...
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... OKI Semiconductor (13) B1-Type Write BCLK CSN AS REGS A18-16 WEHN WELN (z) AD15-0 A BSYN (14) B1-Type Read BCLK CSN AS REGS A18-16 REN (z) AD15-0 A BSYN MEM D (write) A MEM D A (read) PEDL87V3116-02 ML87V3116 D (write) D (read) 36/47 ...
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... Clock/Power Manager 2.7.1 General Description The system clock of the ML87V3116 uses the same pixel clock frequency as display output or a frequency of x2 x8. This clock generates the REFCLK input by a built-in PLL using simple integer ratio n/m (n and m are 1 to 255 reference. Power saving can be achieved by setting to a slower system clock frequency at standby ...
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... OKI Semiconductor 2.7.2 Clock Generation The system clock of the ML87V3116 uses x2 the pixel clock frequency of display output. This clock generates the REFCLK input by a built-in PLL using simple integer ratio n/m (n and m are 1 to 255 • reference. (System clock = n/m The clock for JPEG is generated by the frequency divider of another system, and can be operated even at a slower speed than the system clock ...
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... ° TSTG — Condition VDD1 VSS1 = VSS2 = 0 V VDD2 VSS1 = VSS2 = 0 V VSSP = 0 V TOP — Min io1 PEDL87V3116-02 ML87V3116 Rating Unit –0.3 to +4.6 V –0.3 to +3.6 V –0.3 to +3.6 V –0.3 to VDD1+0.3 V –0.3 to VDD1+0 1.0 W ° C –65 to +150 Range Unit 3 ...
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... VOL2 IOL = 4mA − 10 ILI − 10 ILO IIH VI=VDD1 20 IIL VI=0V -200 IDD1 fope = 54MHz Outputs open IDD2 IDDS VI=0V PEDL87V3116-02 ML87V3116 Typ. Max. Unit - VDD1+0 0.8 V V 0.2 VDD1 V V 0.2 VDD1 V µ A +10 ...
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... CL = 15pF tCK2 tWH2 tWL2 CL = 15pF tHCP tCK2 = tCK2(max) PEDL87V3116-02 ML87V3116 Min. Max. Unit 56.0 MHz ...
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... Host Interface tCK2 tWH2 tWL2 tHCP (b) LCD Interface tCK3 tWH3 tWL3 tS1 tH1 (c) Video Interface Fig. A-1 AC Characteristics PEDL87V3116-02 ML87V3116 VIH VIL VIH VIL VIH VIL tS1 tH1 VDD/2 VDD/2 tPD1 VIH VIL VDD/2 VDD/2 VIH VIL VIH ...
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... LDPn DR7-0 DG7-0 DB7-0 TCP (ACTHED-ACTHST) [TCP] (HLCYC+1) [TCP] Line 0 Line 1 Line 2 Line 3 Line 0 Line 1 Line 2 Line 3 Line 0 Line 1 Line 2 Line 3 (ACTVED-ACTVST) [TLCP] (VFCYC+1) [TLCP] PEDL87V3116-02 ML87V3116 7 8 n-2 n n-2 n n-2 n-1 (FDPnED-FDPnST) 43/47 ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). PEDL87V3116-02 ML87V3116 (Unit: mm) Package material Epoxy resin Lead frame material ...
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... OKI Semiconductor REVISION HISTORY Document Date No. PEDL87V3116-01 Jan. 30, 2004 PEDL87V3116-02 Sep. 21, 2004 Page Previous Current Edition Edition – – Preliminary edition 1 – – PEDL87V3116-02 ML87V3116 Description 45/47 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. PEDL87V3116-02 ML87V3116 Copyright 2004 Oki Electric Industry Co., Ltd. 46/47 ...