tea5764hn-n2 NXP Semiconductors, tea5764hn-n2 Datasheet - Page 26
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tea5764hn-n2
Manufacturer Part Number
tea5764hn-n2
Description
Fm Radio + Rds
Manufacturer
NXP Semiconductors
Datasheet
1.TEA5764HN-N2.pdf
(64 pages)
- Current page: 26 of 64
- Download datasheet (288Kb)
Philips Semiconductors
TEA5764HN_2
Product data sheet
10.3 DAV-C reduced processing mode
If for some reason a valid B block was not received then the next valid A or C’ block is
decoded and the DAVFLG set. The BP and BL registers record the A block history.
When the decoder is synchronized, each decoded block will set the DAVFLG (assuming it
was reset by a read action) and generate an interrupt.
The DAV-C processing mode is very similar to DAV-A mode with the main exception that a
data flag is set only after two new blocks are received. Hence the update rate is reduced
by half.
Fig 10. DAV-A timing diagram, DAV B: with bad blocks detected during sync search
Bus access - read
When the number of blocks detected in the order: ‘bad’ ‘bad’ ‘good’ is 2, synchronization is
achieved if another good block followed by either 0, 1 or 2 bad blocks and another good block
are then received. If the order is 3 bad blocks, no synchronization is achieved and the counters
are reset.
only valid blocks with no errors
are counted as good blocks
sync status bit
BL register
BP register
DAVFLG
bad
B
INTX
good A or C' block detected
1
read intmsk
Rev. 02 — 9 August 2005
21.9 ms
good
C'
x
x
1
bad
C'
D
x
1
1
not synchronized
read BL register
bad
C'
A
x
error correction applied
2
according to SYM bits
1
good
C'
B
x
2
1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
TEA5764HN
good
C'
B
C
2
1
2
synchronized
FM radio + RDS
C
B
001aab472
2
2
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