ml7214a-001 Oki Semiconductor, ml7214a-001 Datasheet - Page 25

• Manufacturer Part Number: ml7214a-001
• Description: Voip Codec
• Manufacturer: Oki Semiconductor

GPIOB[5:0]
This is a general-purpose I/O port B[5:0].
GPIOC[7:0]
This is a general-purpose I/O port C[7:0].
CLKSEL
This is an input-output control input pin of SYNC and BCLK. The pin controls input when it is set to “0” and
output when it is set to “1”.
(Note)
This LSI operates at either SYNC/BCLK that is generated inside the LSI or the clock generated based on
SYNC/BCLK to be input from the outside the LSI. For this reason, if the CLKSEL pin is set to “0”, it is
necessary to constantly input SYNC/BCLK from the time the power supply is truned on regardless of whether
PCM-IF is used or not.
SYNC
This is a 8 kHz synchronous signal I/O pin of PCM signals. When CLKSEL is “0”, constantly input an 8 kHz
clock synchronized with BCLK. When CLKSEL is “1”, this pin outputs an 8 kHz clock synchronized with
BCLK.
and when the register is “1”, short frame synchronization is specified.
BCLK
This is a shift clock I/O pin of a PCM signal.
When CLKSEL is “0”, clock input synchronized with SYNC is necessary. Always input a clock of 128kHz to
2.048MHz after turning on the power. When CLKSEL is “1”, this pin outputs a clock of 2.048 MHz
synchronized with SYNC.
(Remarks) Table 1 shows the input-output control of SYNC and BCLK and the frequencies.
PCMO
This is a PCM signal output pin. A PCM signal is output synchronized with the rise of BCLK or SYNC.
For the output from PCMO, data is output to only the applicable time slot section according to the selected
coding format and the setting of the time slot position and other sections are set to a high-impedance state. If a
PCM interface is not used, PCMO is set to a high impedance state.
(Note)
Be sure to connect a pull-up resistor externally to the PCMO pin, because the pin is an open drain output pin.
Do not use a pull-up voltage greater than the digital power supply voltage (DVDD).
PCMI
This is a PCM signal input pin. The signal is shifted at falling of BCLK and is input from MSB.
If a PCM interface is not used, fix the input to “0” or “1”.
OKI Semiconductor
CLKSEL
“0”
“1”
When the SYNC frame control register (SYNC_SEL) is “0”, long frame synchronization is specified
(8 kHz)
(8 kHz)
Output
SYNC
Input
Table 1 SYNC and BCLK Input-Output Control
(2.048 MHz)
(128 kHz to
2048 kHz)
Output
BCLK
Input
Always input a clock of 128 kHz to 2.048 MHz after start of
power supply.
At power down, “L” is output.
Remarks
FEDL7214_001DIGEST-P
ML7214-001
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