msm7661b Oki Semiconductor, msm7661b Datasheet - Page 30

• Manufacturer Part Number: msm7661b
• Description: Ntsc/pal Digital Video Decoder
• Manufacturer: Oki Semiconductor

¡ Semiconductor
OPERATION MODE SETTING
The video mode includes ;
These modes can be changed by the mode register MRA [4].
The reset state (default) is the external terminal mode.
The following registers can be set in the external terminal mode.
MRA[3]
MRA[2 : 0]
OPERATION CLOCK SETTING
The operation clock settings at ITU-R601 are shown below.
When the double speed clock is used, data can be input at a double speed or at an ordinary speed
by setting the internal register (MRB2) and the clock for the A/D converter.
The internal processing after decimation filter is performed at an ordinary speed.
Input clock
27.0 MHz
27.0 MHz
13.5 MHz
1. Internal terminal mode to be directly set by a dedicated terminal
2. Register setting mode to be specified by setting the internal registers
Input data CLKSEL Pin
27.0 MHz
13.5 MHz
13.5 MHz
input signal mode
input mode
"H"
"L"
"L"
"0" (decimation filter used)
*000:
001:
010:
100:
101:
Register (MRB2)
*0:
1:
"1" (Unused)
"1" (Unused)
Composite video input
S-video input
NTSC ITU-R601
NTSC Square Pixel
MTSC 4Fsc
PAL ITU-R601
PAL Square Pixel
CLKX2O or CLKXO (13.5 MHz)
Clock for A/D converter
CLKXO (13.5 MHz)
CLKX2O (27 MHz)
13.5 MHz
12.27 MHz
14.31818 MHz
13.5 MHz
14.75 MHz
MSM7661B
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