msm7661b Oki Semiconductor, msm7661b Datasheet
msm7661b
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msm7661b Summary of contents
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... MSM7661B NTSC/PAL Digital Video Decoder GENERAL DESCRIPTION The MSM7661B is an LSI device which converts digitally sampled NTSC or PAL video signals to 8-bit format based on ITU-RBT601. The input video signals available are composite video signals and S video signals. The composite video signals are converted to YUV data via a 2-dimensional Y/C separation circuit ...
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... Semiconductor • Multiplex signal recognition (Teletext) Data during vertical blanking is output in 8 bits in Through mode C-bus interface • 3.3 V single power supply (each I/O pin tolerable) • Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: MSM7661B GS-BK) MSM7661B 2/42 ...
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SYNC (CSYNC_L) CLKX2O CLKSEL PLLSEL CLKX2 CLKXO VCO_CP Synchronization Block Decimation YD[7:0] Filter Prologue Block (2Dim. Y/C separate) Line Memory Decimation CD[7:0] (1kbyte) ¥ 2 Filter MODE[3: C-bus Control Logic SCL SDA RESET_L HSY VSYNC_L VVALID SYSSEL HSYNC_L ...
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... Semiconductor PIN CONFIGURATION (TOP VIEW) CD[ CD[1] CD[ CD[3] 5 CD[4] 6 CD[5] 7 CD[6] CD[ CVBS[0] 10 CVBS[1] 11 CVBS[2] 12 CVBS[3] CVBS[ CVBS[5] CVBS[ CVBS[7] 64-Pin Plastic QFP MSM7661B 48 C[0] 47 C[1] 46 C[2] 45 C[3] 44 C[4] 43 C[5] 42 C[6] 41 C[7] 40 Y[0] 39 Y[1] 38 Y[2] 37 Y[3] 36 Y[4] 35 Y[5] 34 Y[6] 33 Y[7] 4/42 ...
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... MHz, "H" Æ ordinary 13.5 MHz Input pin for testing. Normally "L". Internally pulled down. Sleep mode setting pin. Normally "L". Internally pulled down. Input pin for testing. Normally "L". Internally pulled down. MSM7661B MODE[2] 0: NTSC 1: PAL ...
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... NTSC mode : "L", PAL mode : "H" Multiplex signal detect : "H" HLOCK sync detect : "H" Clock output pin Unused. Open normally. Composite sync output. Unused as input pin. Clamp signal timing output pin for A/D converter Clock input pin MSM7661B 6/42 ...
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... DD V — — — STG Symbol Condition Min. V — 3.0 DD GND — — V — 2 — — 0 MSM7661B Rating Unit –0.3 to +4.5 V –0.3 to +5.5 V 800 mW –55 to +150 °C Typ. Max. Unit 3.3 3 — V — — 0 °C 7/42 ...
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... I — DDO CLK = 13.5 MHz I — DDO2 SLEEP ON — DDS SDAV — SDAI — MSM7661B ( 70° 3.3 V ±0 Typ. Max. Unit — — — 0.4 V — +10 mA — 250 — +10 mA 155 190 mA 125 ...
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... D_D2 t CLKSEL : L IS2 t CLKSEL : L IH2 t CLKSEL : L ODX2 t CLKSEL : L OD2X2 t CLKSEL : L OD2 t CLKSEL : L CXD2 t CLKSEL : L CD2 t Rpull_up = 4.7 kW C_SCL t Rpull_up = 4.7 kW L_SCL MSM7661B = 3.3 V ±0 Min. Typ. Max. Unit — 74.07 — ns — 69.84 — ns — 81.5 — ns — 67.8 — — — — — ...
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... Data Line Stable: Data Valid Change of Data Allowed 2 I C-bus Basic Input/Output Timing CLKSEL:L t CLKX2 t IH1 not valid t OD2 2 C-bus interface is as follows ACK t C_SCL MSM7661B t CXD2 t CD2 t IS2 t IH2 not valid not valid t OD2X2 t ODX2 9 P 3-8 ACK Stop Condition 10/42 ...
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... The Y/C is separated by the trap filter if these lines are not correlated (only 2 lines in the case of PAL). In the unadaptive comb filter, the Y/C is always separated by removing the luminance component based on the average of preceding and following lines (when there is the correlation between 3 lines). 2 C-bus. The * mark indicates a default. 13.5 MHz* 12.27 MHz 14.31818 MHz 13.5 MHz 14.75 MHz MSM7661B 11/42 ...
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... High range 3) Coring range select off* 4LBS 5LBS 7LBS 4) Aperture weighting factor select 0* 0.25 0.75 1.5 The profile of these signals can be corrected by coring and aperture correction. 5) Use of pixel position correction circuit Used* Not used 6) AGC loop filter time constant select Slow Factor value 1/1024n MSM7661B 12/42 ...
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... If the demodulation result does not reach a specified level, color killer signals are generated to fix the ACC gain. This functions as an auto color killer control circuit. The UV demodulation result is output as chrominance signals via a low pass filter. 1/64n* 1/n 0 Factor value 1/1024n 1/64n* 1/n 0 MSM7661B 13/42 ...
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... TV, VTR mode select TV mode VTR mode* The TV mode outputs a fixed pixel number per one line and absorbs a jitter that does not appear on the TV receiver normally. The VTR mode outputs the results of decoding in accordance with the HSYNC signal regardless of whether a jitter exists or not. MSM7661B 14/42 ...
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... SYNC tip level. Detect level OMR [5: 136 video in 6) Various modes detection NTSC/PAL detect mode* Multiplex signal detect mode HSYNC synchronization detect mode 7) Output signal phase control MSM7661B 15/42 ...
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... This is the serial interface block based on the I This block functions only as a Slave-Receiver. The external control can set the internal registers (MRA, MRB, HSYT, etc.). 7. Test Control Block This block is used to test this LSI. Normally it is not used standard of Phillips Corporation. MSM7661B 16/42 ...
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... Auto color killer (Chrominance signal level becomes "0" when color burst level is below specified value.) *1: Forced color killer ON (Chrominance signal level is forced to be "0".) *0: (4:2: OFF (Video signal is demodulated and output regardless of synchronization detection .) *1: AUTO (Blue Back is output when synchro- nization is not detected.) MSM7661B (4:1:1) 17/42 ...
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... NTSC Comb filter/trap filter at PAL 3-line comb filter at NTSC 2-line cosine comb filter at PAL 0xC: –4 (–32) to 0xB: +11 (+88) 0xC: –4 (–32) to 0xB: +11 (+88) 0x0: –0 to *0x37:55 to 0xFF:255 0x80: –128 (–512) to 0x7F: +127 (508) 0x8: –8 to 0x7: +7 0x8: –8 to 0x7: +7 MSM7661B 18/42 ...
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... AGC loop filter time constant AGCLF[5:0] AGC reference level 0x8: –8 to 0x7: +7 0x8: –8 to 0x7: +7 *0: OFF Prefilter is not used. *1: Prefilter is used. *00: middle range 01: 10: 11: high range *00: coring off 01: +/–4LSB 10: +/–5LSB 11: +/–7LSB *00: 0 01: 0.25 10: 0.75 11: 1.5 00: slow *01: medium 10: fast 11: fixed 0x20: –32 to 0x1F: +31 MSM7661B 19/42 ...
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... Pedestal clamp is used. (AGC will not operate.) 0x40: –64 to 0x3F: +63 0: *OFF OFF *1: ON 00: 0.5 color burst level *01: 0.25 color burst level 10: 0.125 color burst level 11: 0 (Color killer off) 00: slow *01: medium 10: fast 11: fixed 0x10: –16 to 0x0F: +15 0x80: –180 degrees to 0x7F: 178.6 degrees MSM7661B 20/42 ...
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... Output phase control for data Y (OPCY) <default: 0x00> OPCY[7:3] Undefined OPCY[2] YCbCr 8-bit multiplex output OPCY[1:0] Output phase control for data Y Output phase control for data C (OPCC) <default: 0x00> OPCC[7:2] Undefined OPCC[1:0] Output phase control for data C MSM7661B 00: 80 01: 88 *10: 96 • • 11: 136 *0: ...
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... Semiconductor FUNCTIONAL DESCRIPTION Input Signal Level Input signal is 8 bits in a straight binary format. The recommended input range is shown below. 255 200 NTSC:60 (PAL:63 246 chrominance Iuminance +DC input black level sync 13 input sync-tip level CVBS[7:0] input range MSM7661B reserved 22/42 ...
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... Cr4 C4 Cr6 Cr4 Cr2 Cr3 Cr2 Cr1 Cr0 C0(LSB point point 0 YCbCr 4:1:1 format Y717 Cb718 Y718 Cr718 Y719 MSM7661B ...
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... The timing wave form of HSY/HCL signals, which measure the sync chip and clamp timing for the A/D converter follows. CVBS HSY A/D Converter Support Signal Line control signal The line control signal timing is as follows. CLK CLKO HVALID Y[7:0] Y0 C[7:0] Cb0 Cr0 Y(n) Cb2 Cr2 Cb(n) Line Control Timing MSM7661B COLOR BURST Y(n+1) Cr(n) 24/42 ...
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... Sampling Rate Pixels 13.5 MHz 858 12.27 MHz (SQ) 780 NTSC 14.32 MHz (4FSC) 910 — 13.5 MHz 864 14.75 MHz (SQ) 944 PAL — — Active HBLK Pixels Pixels Front-porch Hsync.Back-porch 720 16 122 640 28 112 768 8 134 720 14 130 768 34 142 MSM7661B Total 138 140 142 144 176 25/42 ...
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... CVBS HVALID HSYNC_L VSYNC_L SYNC (CSYNC_L) VVALID ODD 262 263 264 265 266 267 268 269 270 271 CVBS HVALID HSYNC_L VSYNC_L SYNC (CSYNC_L) VVALID ODD Vertical Synchronizing Signal (NTSC 60 Hz MSM7661B 21 22 283 284 285 26/42 ...
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... CVBS HVALID HSYNC_L SYNC (CSYNC_L) VSYNC_L VVALID ODD 309 310 311 312 313 314 315 316 317 318 CVBS HVALID HSYNC_L SYNC (CSYNC_L) VSYNC_L VVALID ODD Vertical Synchronizing Signal (PAL 50 Hz 336 337 338 MSM7661B 23 24 27/42 ...
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... Semiconductor Horizontal Synchronizing Signal The horizontal synchronizing signal timing is as follows. Y[7:0] HVALID HSYNC_L 60 pixels Horizontal Timing MSM7661B 28/42 ...
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... The write attribute of a register does not match "X" (read/write control bit). The input timing is shown below. SDA MSB SCL Start Condition Data Line Stable: Data Valid Change of Data Allowed 2 I C-bus Basic Input/Output Timing ...... A Data 0 A Description ACK 3-8 C_SCL MSM7661B Data ACK Stop Condition 29/42 ...
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... NTSC Square Pixel 010: MTSC 4Fsc 100: PAL ITU-R601 101: PAL Square Pixel Register (MRB2) Clock for A/D converter "0" (decimation filter used) CLKX2O (27 MHz) "1" (Unused) CLKXO (13.5 MHz) "1" (Unused) CLKX2O or CLKXO (13.5 MHz) MSM7661B 13.5 MHz 12.27 MHz 14.31818 MHz 13.5 MHz 14.75 MHz 30/42 ...
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... ACCLF6 ACCLF5 ACCLF4 C HUE7 HUE6 HUE5 HUE4 D OMR7 OMR6 OMR5 OMR4 E OPCY7 OPCY6 OPCY5 OPCY4 F OPCC7 OPCC6 OPCC5 OPCC4 MSM7661B MRA3 MRA2 MRA1 MRA0 MRB3 MRB2 MRB1 MRB0 HSYT3 HSYT2 HSYT1 HSYT0 STHR3 STHR2 STHR1 STHR0 HSDL3 HSDL2 HSDL1 ...
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... MSM7661B +260 +324 +388 +452 +264 +328 +392 +456 +268 +332 +396 ...
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... –5 –4 –3 –2 – –5 –4 –3 –2 – MSM7661B ...
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... A A –6 + –5 + –4 + –3 + –2 + –1 + +16 +32 +48 +17 +33 +49 +18 +34 +50 +19 +35 +51 +20 +36 +52 +21 +37 +53 +22 +38 +54 +23 +39 +55 +24 +40 +56 +25 +41 +57 +26 +42 +58 +27 +43 +59 +28 +44 +60 +29 +45 +61 +30 +46 +62 +31 +47 +63 MSM7661B 34/42 ...
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... MSM7661B +90.0 +112.5 +135.0 +157.5 +91.4 +113.9 +136.4 +158.9 +92.8 +115.3 +137.8 +160.3 +94.2 +116.7 +139.2 +161.7 +95.6 +118.1 +140.6 +163.1 +97.0 +119.5 +142.0 +164.5 +98.4 +120.9 +143.4 +165.9 +99.8 +122.3 +144.8 +167.3 +101 ...
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... Semiconductor Filter Characteristics Band Pass Filter (NTSC ITU-R601) 0 –20 –40 –60 –80 –100 –20 –40 –60 –80 –100 Frequency [MHz] Band Pass Filter (PAL ITU-R601 Frequency [MHz] MSM7661B 36/42 ...
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... Semiconductor 0 –20 –40 –60 –80 –100 –20 –40 –60 –80 –100 0 1 Trap Filter (NTSC ITU-R601 Frequency [MHz] Trap Filter (PAL ITU-R601 Frequency [MHz] MSM7661B 6 6 37/42 ...
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... Semiconductor 0 –20 –40 –60 –80 –100 –20 –40 –60 –80 –100 0 1 Pre Filter Frequency [MHz] Sharp Filter Frequency [MHz] MSM7661B 6 6 38/42 ...
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... Semiconductor 0 –20 –40 –60 –80 –100 The characteristics of the various filters shown above are based on design data. Decimation Filter Frequency [MHz] MSM7661B 12 39/42 ...
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... Mode setting Video signal: NTSC-composite CLKX2: 27 MHz Video in LPF1 A/D C Input circuit A/D C: CXD1179Q (SONY) LPF1: 628LJN-1471 (TOKO Controller 8 CVBS0 CVBS7 8 CD0 MSM7661B CD7 CLKXO2 SYNC VC0_CP CLKX2 OSC Dip SW MSM7661B 3 Frame 8 memory or image LSI HVALID VVALID ODD CLKXO 3.3 V 40/42 ...
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... Mode setting Video signal: NTSC-composite CLKX2: 13.5 MHz Video in LPF1 A/D C Input circuit A/D C: upc659 (NEC) LPF1: 628LJN-1471 (TOKO Controller 8 CVBS0 CVBS7 8 CD0 MSM7661B CD7 CLKXO2 SYNC VC0_CP CLKX2 OSC Dip SW MSM7661B 3 Frame 8 memory or image LSI HVALID VVALID ODD CLKXO 3.3 V 41/42 ...
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... Semiconductor PACKAGE OUTLINES AND DIMENSIONS 64-Pin Plastic QFP MSM7661B (Unit : mm) 42/42 ...