msm7731-01 Oki Semiconductor, msm7731-01 Datasheet - Page 33

• Manufacturer Part Number: msm7731-01
• Description: Multifunction Pcm Codec Voice Signal Processor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
(5) CR4 (Line echo canceler settings)
B7 .......... "Through mode" control 1: "through mode", 0: normal mode (echo cnaceler operation)
B6, B5 ... Reserved bits
B4 .......... Howling detector control
B3 .......... Center clip control
B2 .......... Coefficient update control
B1 .......... Attenuator control
B0 .......... Gain controller
CR4
Initial value
This is the "through mode" control bit for the line echo canceler. In the "through
mode", RinL and SinL data is output directly to RoutL and SoutL respectively.
Coefficients are not reset.
This bit is internally ORed with the LTHR pin.
This bit controls the function to detect and cancel the howling that occurs in an
acoustic system such as a handsfree communication system.
This bit is internally ORed with the LHD pin.
When the SoutL output of the line echo canceler is –57 dBm0 or less, the center
clip function forcibly sets it to the minimum positive value.
This bit selects whether the adaptive FIR filter (AFR) coefficients for the line
echo canceler will be updated.
This bit is internally ORed with the LHLD pin.
This bit turns ON or OFF the ATT function to prevent howling by means of
attenuators (ATTsL, ATTrL) provided in the RinL input and SoutL output of
the line echo canceler.
If input is only to RinL, the ATT for SoutL (ATTsL) is activated. If input is only
to SinL, or if there is input to both SinL and RinL, the ATT for RinL input
(ATTrL) is activated. The ATT value of each attenuator is approximately 6 dB.
This bit is internally ORed with the LATT pin.
This bit turns ON or OFF the gain control function to control the RinL input
level and prevent howling by means of a gain controller (GainL) provided in the
RinL input of the line echo canceler.
The gain controller adjusts the RIN input level when it is –10 dBm0 or above,
and it has the control range of 0 to –8.5 dB.
This bit is internally ORed with the LGC pin.
LTHR
B7
0
B6
—
0
B5
—
0
Modification of initial values is inhibited
1: OFF,
1: ON,
1: fixed coefficients,
1: ATT OFF,
1: GC OFF,
LHD
B4
0
LCLP
B3
0
LHLD
B2
0
0: ON
0: updated coefficients
0: ATT ON
0: OFF
0: GC ON
LATT
B1
0
MSM7731-01
LGC
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B0
0