msm7731-01 Oki Semiconductor, msm7731-01 Datasheet - Page 28

• Manufacturer Part Number: msm7731-01
• Description: Multifunction Pcm Codec Voice Signal Processor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
(1) CR0 (basic operating mode settings)
B7 .......... Power-down reset
B6 .......... Reset control
B5 .......... Line CODEC I/O control
B4 .......... SYNC, BCLK output control
B3 .......... PCM I/O control
B2 .......... PCME I/O control
CR0
Initial value (*4)
During power-down reset, this device enters the power-down state. At this
time, all control register bits and internal variables are reset. After power-down
reset is released, this device enters the initial mode. This bit is internally ORed
with the inverted PDN/RST signal.
At reset, the coefficients for the echo canceler and noise canceler are reset.
Control register contents are preserved. While reset is being processed, there
is no sound. Use this bit in cases where the echo path changes (due to line
switching during a telephone conversation, etc.), or when resuming telephone
communicaion. This bit is internally ORed with the inverted RST signal.
When OFF, the line CODEC is in the power-down state, the line CODEC output
pin is at high impedance and line CODEC input pin is internally processed as
an idle pattern input. This bit is internally ORed with the LINEEN pin. When
the line CODEC is not used, this control results in low consumption of electrical
power.
This bit can only be set to "0" or "1" during power-down reset and the initial
mode.
When OFF, the SYNC and BCLK output pins are in the high impedance state.
This control is valid when the CLKSEL pin is at a logic "0" and has selected the
internal clock mode. When the SYNC and BCLK clocks are not used externally,
this control results in low consumption of electrical power.
This bit can only be set to "0" or "1" during power-down reset and the initial
mode.
When OFF, the PCMO output pin is in the high impedance state and the PCMI
input pin is internally processed as an idle pattern input. When the line digital
interface is not used, this control results in low consumption of electrical power.
This bit can only be set to "0" or "1" during power-down reset and the initial
mode.
When OFF, the PCMEO output pin is in the high impedance state and the
PCMEI input pin is internally processed as an idle pattern input. When not
used for message output and memo recording, this control results in low
consumption of electrical power.
This bit can only be set to "0" or "1" during power-down reset and the initial
mode.
Note: *4. Initial values are the values set when reset is activated by the PDN/
PDN/RST
B7
0
RST pin. (Initial values are also set in the same manner, except for
CR0-B7, when reset by the PDN/RST bit of B7).
RST
B6
0
LINEEN
B5
0
0: power-on,
0: normal operation,
0: ON,
0: ON,
0: ON,
0: ON,
CLKEN
B4
0
PCMEN
B3
0
PCMEEN
B2
0
1: reset
1: OFF
1: power-down reset
1: OFF
1: OFF
1: OFF
MCUSEL
OPE
B1
0
MSM7731-01
ECSEL
OPE
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B0
0