msm9225 Oki Semiconductor, msm9225 Datasheet - Page 4

• Manufacturer Part Number: msm9225
• Description: Can Controller Area Network Controller
• Manufacturer: Oki Semiconductor

¡ Semiconductor
PIN DESCRIPTIONS
Symbol
CS
A7-0
AD7-0
/D7-0
PWR
RPD/SRW
PALE
SDI
SDO
SCLK
PRDY
/SWAIT
41-44,
31-38
Pin
1-4
10
26
27
16
9
7
5
8
Type
I/O
O
O
I
I
I
I
I
I
I
Chip select pin. When "L", PALE, PWR, PRD/SRW, SCLK and SDO pins are valid.
Address bus pins (when using separate buses). If used with a multiplexed bus or if
used in the serial mode, fix these pins at "H" or "L" levels.
Multiplexed bus: Address/data pins
Separate buses: Data pins
If used in the serial mode, fix these pins at "H" or "L" levels.
Write input pin during parallel mode. Data is captured when this pin is at a "L" level.
If used in the serial mode, fix this pin at a "H" or "L" level.
Parallel mode: Read signal pin.
When at a "L" level, data is output from the data pin.
Serial mode: Read/write signal pin.
When at a "H" level, data is output from the SDO pin.
When at a "L" level, the SDO pin is at high impedance, and data is captured beginning
with the second byte of data input from the SDI pin.
Address latch signal pin.
When at a "H" level, addresses are captured.
If used in the parallel mode and the address latch signal is unnecessary or in the
serial mode, fix this pin at a "H" or "L" level.
Serial data input pin.
Addresses (1st byte) and data (beginning from the 2nd byte) are input to this pin,
LSB first. If used in the parallel mode, fix this pin at a "H" or "L" level.
Serial data output pin.
When the CS pin is at a "H" level, this pin is at high impedance. When CS is at a "L"
level, data is output from this pin LSB first.
If used in the parallel mode, fix this pin at a "H" or "L" level.
Shift clock input pin for serial data.
At the rising edge of the shift clock, SDI pin data is captured. At the falling edge, data
is output from the SDO pin.
Ready output pin.
If the microcontroller's bus cycle is fast, a signal is output to extend the bus cycle
until the internal access is completed.
Parallel mode
Serial mode
Internal access in progress
"L" level output
"H" level output
Description
After completion of access
High impedance output
"L" level output
MSM9225
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