msm9225 Oki Semiconductor, msm9225 Datasheet - Page 19

• Manufacturer Part Number: msm9225
• Description: Can Controller Area Network Controller
• Manufacturer: Oki Semiconductor

If setting is :
Sampling point = 5 BTL cycle
If f
Therefore 1 bit time is :
6. Communication input/output control register (TIOC: 2Fhex)
¡ Semiconductor
then the bit timing is as follows
osc
(3) Bit timing
This register sets the communication mode and output buffer format.
Writing to the TIOC bit is enabled, when the INIT bit of the CAN control register (CANC:
0Ehex) is "1".
The bit configuration is as follows:
= 16 MHz, then 1 BTL cycle is :
Bit timing is set by CAN bus timing registers 0 and 1. The relationship between 1 bit time
of a message and a CAN bus timing (the MSM9225 register) is as follows:
Sync segment
SJW 1
TSEG 1
TSEG 2
SJW 2
1 bit time
BTR0 = "01000001" ...SJWB = "0" SJWA = "1" BRP5-0 = "000001"
BTR1 = "00000001"...TSEG2 = "000" TSEG1 = "0001"
8 BTL cycle = 8 ¥ 0.25 ms = 2.0 ms
(= 500 Kb/s)
BTL cycle = 2 ¥ (2
SYNC-SEG
1BTL
cycle
(BTR0 : SJWB/A)
PROP-SEG
SJW1
1 BTL cycle (fixed)
8 BTL cycle
2 BTL cycle
2 BTL cycle
1 BTL cycle
2 BTL cycle
5
¥ 0 + 2
4
(BTR1 : TSEG13-10)
¥ 0 + 2
PHASE-SEG1
TSEG1
3
1 bit time
¥ 0 + 2
Sampling
2
point
¥ 0 + 2
(BTR1 : TSEG22-20)
1
¥ 0 + 1 + 1) / 16 MHz = 0.25 ms
TSEG2
PHASE-SEG2
(= SJW1)
SJW2
MSM9225
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