co711ag Connect One Ltd., co711ag Datasheet - Page 15

• Manufacturer Part Number: co711ag
• Description: Ichip? Co710ag And Ichipsec? Co711ag Internet Controllers? Are High-performance, Firmware-based Intelligent Peripheral Devices That Provide Internet Connectivity Solutions For A Wide Range Of Embedded Devices.
• Manufacturer: Connect One Ltd.

Connect One
5 Hardware Interface
iChip CO710AG/CO711AG interface a host CPU in one of two methods: Serial or
Parallel. The actual interface depends on the state of the –SER/PAR pin.
5.1 Serial Host Interface
The host interface is a serial DTE interface. Speeds of 2400, 4800, 9600, 19200,
38400, 57600, 115200 and 230400 bps are supported in the following data format:
5.2 Parallel Host Interface
In Parallel interface mode, iChip connects to a host CPU through a parallel interface
using a PAL (i.e., Altera “EPM7032AEC44”). The host parallel BUS may be an
80x86 (Intel) or a 68K (Motorola) BUS. With some small changes to the PAL, the
user may customize an interface to any other BUS architecture. iChip is connected to
the interface PAL through the following signals:
Notes:
iChip CO710AG/iChipSec CO711AG Data Sheet
•
• -RD:
• -WR:
•
• -PRES: Parallel reset. When LOW, generates a reset signal to the parallel
• -PERR: Parallel error. When LOW, indicates a parallel interface error.
• POBE: Parallel Output Buffer Empty. When HIGH, indicates that the output
• PIBF:
PCS:
D0-D7: Bi-directional data BUS.
Table 5-1 Host Data Format
1: When hardware flow control is enabled, the iChip transmitter will add an
2: Parallel interface mode is available only from iChip firmware version 8.01.
additional stop bit.
Parity
None
Parallel chip select signal. When PCS is HIGH, the PAL is selected.
When –RD is LOW, iChip reads data from PAL.
When –WR is LOW, iChip writes data to PAL.
interface.
buffer is empty and iChip may send additional data to host. When
iChip sends a data byte, this signal goes LOW until the host reads the
data.
Parallel Input Buffer Full. When HIGH, indicates that the input
buffer is full and iChip may read a data byte from the host. When
iChip reads the data byte, this signal goes LOW.
Data Length
(No. of Bits)
8
2
Stop Bits
No. of
1
1
Transmission
(No. of Bits)
Hardware Interface
Length
10
5-1