ml7033 Oki Semiconductor, ml7033 Datasheet - Page 26

• Manufacturer Part Number: ml7033
• Description: Dual-channel Line Card Codec
• Manufacturer: Oki Semiconductor

Control Registers Functional Description
CR0 (Basic operating mode)
B7
B6
B5
B4
B3
B2
B1, B0
1 Semiconductor
default
CR0
*1 forced to be default by the RESET pin = logic “0”.
MODE1
FILTER1SEL
0/1
0
0
bit
0
0
1
1
*1
*1
B7
… Transmit and receive filter select for CH1
… Transmit and receive filter select for CH2
… MCK frequency select
… Frame synchronizing scheme select
… PCM companding law select
… PCM companding law select
… Power saving control
0
0 : ITU-T G.714 filter
0 : ITU-T G.714 filter
Refer to Figure 3.
0 : 8-bit PCM mode
“1” is selected, a setting with the ALAW (CR0-B2) bit is ignored.
When the LIN (CR0-B3) is “1”, a setting with this bit is ignored.
The MODE1 (CR0-B1) bit is for channel 2, and the MODE0 (CR0-B0) bit is for channel 1.
In power saving mode, power for the corresponding channel is turned off except for the last
output stage of the PCMOUT pin. The power saving mode differs from the power-down
mode controlled by the PDN pin in the following aspects;
As in power-down mode, the power saving mode does not initialize control registers and
read and write of control registers are possible in the power saving mode. The power-down
mode setting by the PDN pin takes precedence over the power saving mode.
-
-
-
MODE0
Possible to control a state for an individual channel independently
The last stage of the PCMOUT pin is operational, and outputs ‘positive zero’ PCM code
in the 8-bit PCM mode or ‘zero’ PCM code in the 14-bit Linear PCM mode during the
assigned time slot.
Debounce timer and hold timer are valid.
0/1
0
0
bit
0
1
0
1
*1
*1
FILTER2SEL
Table 7 Mode Settings for CH1 and CH2
B6
0
PDN
pin
0
1
0
1
1
1
1
MCKSEL
RESET
pin
B5
0
0
1
1
1
1
1
0
0 : Power saving mode
0 : 2.048 MHz
1 : wideband filter for V.90 data modem application
1 : wideband filter for V.90 data modem application
1 : 14-bit linear PCM (2’s complement) mode
Power of Channel
OFF
OFF
OFF
SHORT
CH2
OFF
OFF
ON
ON
0 : -law
B4
0
*2
*2
*2
0 : Long frame SYNC 1 : Short frame SYNC
*2 The last output stage is powered.
OFF
OFF
OFF
CH1
OFF
OFF
ON
ON
1 : 4.096 MHz
LIN
B3
*2
*2
*2
0
1 : A-law
1 : Normal operation
Read/Write possible
Read/Write possible
Read/Write possible
Read/Write possible
Read/Write possible
Initialized to default
Initialized to default
ALAW
B2
0
Register
MODE1
B1
0
FEDL7033-02
MODE0
ML7033
B0
0
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