ml7033 Oki Semiconductor, ml7033 Datasheet - Page 21

• Manufacturer Part Number: ml7033
• Description: Dual-channel Line Card Codec
• Manufacturer: Oki Semiconductor

*1
*2
F2_1, F1_1, F0_1, F2_2, F1_2, F0_2
The F2_n, F1_n and F0_n pins are data outputs used when the SLIC connected to the corresponding channel is
an Intersil RSLIC
the F2_n, F1_n, and F0_n register bits (CR6-B7 to B5 and CR13-B7 to B5). By inputting these outputs directly
into the corresponding input pin of the SLIC device, the SLIC operating mode selection is possible.
Even in the power-down state with the PDN pin is asserted, these pins remain functional.
E0_1, E0_2
The E0_n pins are the detector mode selection data outputs. These pins are used when the SLIC connected to the
corresponding channel is an Intersil RSLIC
determined by the E0_n bit (CR6-B2/CR13-B2), the output level changes in 20 s (= hold timer) in the power-
on mode with the PDN pin = logic “1” and in 200 ns in the power-down mode with the PDN pin = logic “0”
after the change of E0_n bit (CR6-B2 /CR13-B2). Refer to Figure 6 for information.
What event is actually detected by the SLIC is determined by the combination of the F2_n, F1_n, F0_n and E0_n
pins. Refer to Table 6 for more information. By connecting the output directly into the corresponding input pin
of the SLIC device, detector mode selection in the SLIC is possible. Even in the power-down state with the PDN
pin = logic “0”, this pin remains functional. However, the hold timer is ignored in this state.
1 Semiconductor
The data will be ‘H’ by an external pull-up resistor.
Output impedance = about 50 k
PDN pin
PDN
pin
0
1
1
1
1
Table 4 State of PCMOUT in 14-bit Linear PCM Mode with LIN (CR0-B3) bit = “1”
0
1
1
1
1
MODE1
0/1
bit
0
0
1
1
MODE1 bit
TM
MODE0
series device. The output levels from the F2_n, the F1_n and F0_n pins are determined by
0/1
0
0
1
1
0/1
bit
0
1
0
1
Operate
Operate
GSX1
Hi-Z
Hi-Z
Hi-Z
MODE0 bit
pin
Table 5 State of Analog Output Pins
0/1
0
1
0
1
Operate
Operate
GSX2
Hi-Z
Hi-Z
Hi-Z
pin
TM
ALAW bit
series device. Though the output level from the E0_n pin is
0/1
Operate
Operate
AOUT1
Hi-Z
Hi-Z
Hi-Z
pin
Operate
Operate
AOUT2
CH2 PCM Data
Hi-Z
Hi-Z
Hi-Z
pin
Operate
Operate
ALL “0”
ALL “0”
Hi-Z *1
Operate
Operate
Operate
Hi-Z
Hi-Z
SG
pin
AG level *2
AG level *2
Operate
Operate
Operate
SGC
pin
CH1 PCM Data
Operate
Operate
ALL “0”
ALL “0”
Hi-Z *1
Interface
Operate
Operate
Operate
Operate
Operate
FEDL7033-02
MCU
ML7033
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